2 * VGIC MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/bsearch.h>
16 #include <linux/kvm.h>
17 #include <linux/kvm_host.h>
18 #include <kvm/iodev.h>
19 #include <kvm/arm_vgic.h>
22 #include "vgic-mmio.h"
24 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
25 gpa_t addr, unsigned int len)
30 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
31 gpa_t addr, unsigned int len)
36 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
37 unsigned int len, unsigned long val)
43 * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
44 * of the enabled bit, so there is only one function for both here.
46 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
47 gpa_t addr, unsigned int len)
49 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
53 /* Loop over all IRQs affected by this read */
54 for (i = 0; i < len * 8; i++) {
55 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
60 vgic_put_irq(vcpu->kvm, irq);
66 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
67 gpa_t addr, unsigned int len,
70 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
73 for_each_set_bit(i, &val, len * 8) {
74 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
76 spin_lock(&irq->irq_lock);
78 vgic_queue_irq_unlock(vcpu->kvm, irq);
80 vgic_put_irq(vcpu->kvm, irq);
84 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
85 gpa_t addr, unsigned int len,
88 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
91 for_each_set_bit(i, &val, len * 8) {
92 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
94 spin_lock(&irq->irq_lock);
98 spin_unlock(&irq->irq_lock);
99 vgic_put_irq(vcpu->kvm, irq);
103 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
104 gpa_t addr, unsigned int len)
106 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
110 /* Loop over all IRQs affected by this read */
111 for (i = 0; i < len * 8; i++) {
112 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
117 vgic_put_irq(vcpu->kvm, irq);
123 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
124 gpa_t addr, unsigned int len,
127 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
130 for_each_set_bit(i, &val, len * 8) {
131 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
133 spin_lock(&irq->irq_lock);
135 if (irq->config == VGIC_CONFIG_LEVEL)
136 irq->soft_pending = true;
138 vgic_queue_irq_unlock(vcpu->kvm, irq);
139 vgic_put_irq(vcpu->kvm, irq);
143 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
144 gpa_t addr, unsigned int len,
147 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
150 for_each_set_bit(i, &val, len * 8) {
151 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
153 spin_lock(&irq->irq_lock);
155 if (irq->config == VGIC_CONFIG_LEVEL) {
156 irq->soft_pending = false;
157 irq->pending = irq->line_level;
159 irq->pending = false;
162 spin_unlock(&irq->irq_lock);
163 vgic_put_irq(vcpu->kvm, irq);
167 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
168 gpa_t addr, unsigned int len)
170 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
174 /* Loop over all IRQs affected by this read */
175 for (i = 0; i < len * 8; i++) {
176 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
181 vgic_put_irq(vcpu->kvm, irq);
187 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
188 bool new_active_state)
190 spin_lock(&irq->irq_lock);
192 * If this virtual IRQ was written into a list register, we
193 * have to make sure the CPU that runs the VCPU thread has
194 * synced back LR state to the struct vgic_irq. We can only
195 * know this for sure, when either this irq is not assigned to
196 * anyone's AP list anymore, or the VCPU thread is not
197 * running on any CPUs.
199 * In the opposite case, we know the VCPU thread may be on its
200 * way back from the guest and still has to sync back this
201 * IRQ, so we release and re-acquire the spin_lock to let the
202 * other thread sync back the IRQ.
204 while (irq->vcpu && /* IRQ may have state in an LR somewhere */
205 irq->vcpu->cpu != -1) /* VCPU thread is running */
206 cond_resched_lock(&irq->irq_lock);
208 irq->active = new_active_state;
209 if (new_active_state)
210 vgic_queue_irq_unlock(vcpu->kvm, irq);
212 spin_unlock(&irq->irq_lock);
216 * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
217 * is not queued on some running VCPU's LRs, because then the change to the
218 * active state can be overwritten when the VCPU's state is synced coming back
221 * For shared interrupts, we have to stop all the VCPUs because interrupts can
222 * be migrated while we don't hold the IRQ locks and we don't want to be
223 * chasing moving targets.
225 * For private interrupts, we only have to make sure the single and only VCPU
226 * that can potentially queue the IRQ is stopped.
228 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
230 if (intid < VGIC_NR_PRIVATE_IRQS)
231 kvm_arm_halt_vcpu(vcpu);
233 kvm_arm_halt_guest(vcpu->kvm);
236 /* See vgic_change_active_prepare */
237 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
239 if (intid < VGIC_NR_PRIVATE_IRQS)
240 kvm_arm_resume_vcpu(vcpu);
242 kvm_arm_resume_guest(vcpu->kvm);
245 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
246 gpa_t addr, unsigned int len,
249 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
252 vgic_change_active_prepare(vcpu, intid);
253 for_each_set_bit(i, &val, len * 8) {
254 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
255 vgic_mmio_change_active(vcpu, irq, false);
256 vgic_put_irq(vcpu->kvm, irq);
258 vgic_change_active_finish(vcpu, intid);
261 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
262 gpa_t addr, unsigned int len,
265 u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
268 vgic_change_active_prepare(vcpu, intid);
269 for_each_set_bit(i, &val, len * 8) {
270 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
271 vgic_mmio_change_active(vcpu, irq, true);
272 vgic_put_irq(vcpu->kvm, irq);
274 vgic_change_active_finish(vcpu, intid);
277 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
278 gpa_t addr, unsigned int len)
280 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
284 for (i = 0; i < len; i++) {
285 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
287 val |= (u64)irq->priority << (i * 8);
289 vgic_put_irq(vcpu->kvm, irq);
296 * We currently don't handle changing the priority of an interrupt that
297 * is already pending on a VCPU. If there is a need for this, we would
298 * need to make this VCPU exit and re-evaluate the priorities, potentially
299 * leading to this interrupt getting presented now to the guest (if it has
300 * been masked by the priority mask before).
302 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
303 gpa_t addr, unsigned int len,
306 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
309 for (i = 0; i < len; i++) {
310 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
312 spin_lock(&irq->irq_lock);
313 /* Narrow the priority range to what we actually support */
314 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
315 spin_unlock(&irq->irq_lock);
317 vgic_put_irq(vcpu->kvm, irq);
321 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
322 gpa_t addr, unsigned int len)
324 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
328 for (i = 0; i < len * 4; i++) {
329 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
331 if (irq->config == VGIC_CONFIG_EDGE)
332 value |= (2U << (i * 2));
334 vgic_put_irq(vcpu->kvm, irq);
340 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
341 gpa_t addr, unsigned int len,
344 u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
347 for (i = 0; i < len * 4; i++) {
348 struct vgic_irq *irq;
351 * The configuration cannot be changed for SGIs in general,
352 * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
353 * code relies on PPIs being level triggered, so we also
354 * make them read-only here.
356 if (intid + i < VGIC_NR_PRIVATE_IRQS)
359 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
360 spin_lock(&irq->irq_lock);
362 if (test_bit(i * 2 + 1, &val)) {
363 irq->config = VGIC_CONFIG_EDGE;
365 irq->config = VGIC_CONFIG_LEVEL;
366 irq->pending = irq->line_level | irq->soft_pending;
369 spin_unlock(&irq->irq_lock);
370 vgic_put_irq(vcpu->kvm, irq);
374 static int match_region(const void *key, const void *elt)
376 const unsigned int offset = (unsigned long)key;
377 const struct vgic_register_region *region = elt;
379 if (offset < region->reg_offset)
382 if (offset >= region->reg_offset + region->len)
388 /* Find the proper register handler entry given a certain address offset. */
389 static const struct vgic_register_region *
390 vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
393 return bsearch((void *)(uintptr_t)offset, region, nr_regions,
394 sizeof(region[0]), match_region);
398 * kvm_mmio_read_buf() returns a value in a format where it can be converted
399 * to a byte array and be directly observed as the guest wanted it to appear
400 * in memory if it had done the store itself, which is LE for the GIC, as the
401 * guest knows the GIC is always LE.
403 * We convert this value to the CPUs native format to deal with it as a data
406 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
408 unsigned long data = kvm_mmio_read_buf(val, len);
414 return le16_to_cpu(data);
416 return le32_to_cpu(data);
418 return le64_to_cpu(data);
423 * kvm_mmio_write_buf() expects a value in a format such that if converted to
424 * a byte array it is observed as the guest would see it if it could perform
425 * the load directly. Since the GIC is LE, and the guest knows this, the
426 * guest expects a value in little endian format.
428 * We convert the data value from the CPUs native format to LE so that the
429 * value is returned in the proper format.
431 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
438 data = cpu_to_le16(data);
441 data = cpu_to_le32(data);
444 data = cpu_to_le64(data);
447 kvm_mmio_write_buf(buf, len, data);
451 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
453 return container_of(dev, struct vgic_io_device, dev);
456 static bool check_region(const struct vgic_register_region *region,
459 if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
461 if ((region->access_flags & VGIC_ACCESS_32bit) &&
462 len == sizeof(u32) && !(addr & 3))
464 if ((region->access_flags & VGIC_ACCESS_64bit) &&
465 len == sizeof(u64) && !(addr & 7))
471 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
472 gpa_t addr, int len, void *val)
474 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
475 const struct vgic_register_region *region;
476 struct kvm_vcpu *r_vcpu;
479 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
480 addr - iodev->base_addr);
481 if (!region || !check_region(region, addr, len)) {
486 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
487 data = region->read(r_vcpu, addr, len);
488 vgic_data_host_to_mmio_bus(val, len, data);
492 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
493 gpa_t addr, int len, const void *val)
495 struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
496 const struct vgic_register_region *region;
497 struct kvm_vcpu *r_vcpu;
498 unsigned long data = vgic_data_mmio_bus_to_host(val, len);
500 region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
501 addr - iodev->base_addr);
505 if (!check_region(region, addr, len))
508 r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
509 region->write(r_vcpu, addr, len, data);
513 struct kvm_io_device_ops kvm_io_gic_ops = {
514 .read = dispatch_mmio_read,
515 .write = dispatch_mmio_write,
518 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
521 struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
527 len = vgic_v2_init_dist_iodev(io_device);
529 #ifdef CONFIG_KVM_ARM_VGIC_V3
531 len = vgic_v3_init_dist_iodev(io_device);
538 io_device->base_addr = dist_base_address;
539 io_device->redist_vcpu = NULL;
541 mutex_lock(&kvm->slots_lock);
542 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
543 len, &io_device->dev);
544 mutex_unlock(&kvm->slots_lock);