/*
 * Copyright 2014 Broadcom Corporation.  All rights reserved.
 *
 * Unless you and Broadcom execute a separate written software license
 * agreement governing use of this software, this software is licensed to you
 * under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,cygnus";
	model = "Broadcom Cygnus SoC";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
	};

	/include/ "bcm-cygnus-clock.dtsi"

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus", "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		wdt@18009000 {
			 compatible = "arm,sp805" , "arm,primecell";
			 reg = <0x18009000 0x1000>;
			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			 clocks = <&axi81_clk>;
			 clock-names = "apb_pclk";
		};
	};

	uart3: serial@18023000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18023000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <100000000>;
		clocks = <&axi81_clk>;
		status = "okay";
	};

	uart0: serial@18020000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x18020000 0x100>;
		reg-shift = <2>;
		reg-io-width = <4>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&axi81_clk>;
		clock-frequency = <100000000>;
		status = "okay";
	};

	gic: interrupt-controller@19021000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0x19021000 0x1000>,
		      <0x19020100 0x100>;
	};

	L2: l2-cache {
		compatible = "arm,pl310-cache";
		reg = <0x19022000 0x1000>;
		cache-unified;
		cache-level = <2>;
	};

	timer@19020200 {
		compatible = "arm,cortex-a9-global-timer";
		reg = <0x19020200 0x100>;
		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&periph_clk>;
	};

};