+/* CPU interrupt offsets */
+#define CPU_INT_GIC 2
+#define CPU_INT_EHCI 2
+#define CPU_INT_UART0 4
+#define CPU_INT_UART1 4
+#define CPU_INT_NET 6
+
+/* GIC interrupt offsets */
+#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
+#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
+#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
+#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)