devicetree: document Ingenic SoC interrupt controller binding

[cascardo/linux.git] / Documentation / devicetree / bindings / interrupt-controller / ingenic,intc.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
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+Ingenic SoC Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ingenic,<socname>-intc". Valid strings are:
+    ingenic,jz4740-intc
+    ingenic,jz4770-intc
+    ingenic,jz4775-intc
+    ingenic,jz4780-intc
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+- interrupt-parent : phandle of the CPU interrupt controller.
+- interrupts : Specifies the CPU interrupt the controller is connected to.
+
+Example:
+
+intc: interrupt-controller@10001000 {
+       compatible = "ingenic,jz4740-intc";
+       reg = <0x10001000 0x14>;
+
+       interrupt-controller;
+       #interrupt-cells = <1>;
+
+       interrupt-parent = <&cpuintc>;
+       interrupts = <2>;
+};