ath10k: remove deprecated firmware API 1 support

[cascardo/linux.git] / Documentation / memory-barriers.txt

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index ae9d306..3729cbe 100644 (file)
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -1270,7 +1270,7 @@ TRANSITIVITY
 
 Transitivity is a deeply intuitive notion about ordering that is not
 always provided by real computer systems.  The following example
-demonstrates transitivity (also called "cumulativity"):
+demonstrates transitivity:
 
        CPU 1                   CPU 2                   CPU 3
        ======================= ======================= =======================
@@ -1372,6 +1372,10 @@ is possible:
 
        r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
 
+As an aside, the following outcome is also possible:
+
+       r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
+
 Although cpu0(), cpu1(), and cpu2() will see their respective reads and
 writes in order, CPUs not involved in the release-acquire chain might
 well disagree on the order.  This disagreement stems from the fact that
@@ -1546,7 +1550,7 @@ of optimizations:
      the following:
 
        a = 0;
-       /* Code that does not store to variable a. */
+       ... Code that does not store to variable a ...
        a = 0;
 
      The compiler sees that the value of variable 'a' is already zero, so
@@ -1558,7 +1562,7 @@ of optimizations:
      wrong guess:
 
        WRITE_ONCE(a, 0);
-       /* Code that does not store to variable a. */
+       ... Code that does not store to variable a ...
        WRITE_ONCE(a, 0);
 
  (*) The compiler is within its rights to reorder memory accesses unless