Merge remote-tracking branch 'asoc/fix/rt5645' into asoc-linus

[cascardo/linux.git] / arch / arm / boot / dts / imx6qdl-gw52xx.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 18cd411..9fa8a10 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -151,6 +151,21 @@
        status = "okay";
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                         <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi3 {
+       fsl,spi-num-chipselects = <1>;
+       cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3>;
+       status = "okay";
+};
+
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
@@ -275,6 +290,18 @@
        status = "okay";
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &pwm4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm4>;
@@ -338,6 +365,15 @@
                        >;
                };
 
+               pinctrl_ecspi3: escpi3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
+                               MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
+                               MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
+                               MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x100b1
+                       >;
+               };
+
                pinctrl_enet: enetgrp {
                        fsl,pins = <
                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
@@ -429,6 +465,18 @@
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_pwm4: pwm4grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1