Merge tag 'kvm-arm-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm...

[cascardo/linux.git] / arch / arm / kvm / interrupts_head.S

diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 76af930..98c8c5b 100644 (file)
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -1,4 +1,5 @@
 #include <linux/irqchip/arm-gic.h>
+#include <asm/assembler.h>
 
 #define VCPU_USR_REG(_reg_nr)  (VCPU_USR_REGS + (_reg_nr * 4))
 #define VCPU_USR_SP            (VCPU_USR_REG(13))
@@ -420,15 +421,23 @@ vcpu      .req    r0              @ vcpu pointer always in r0
        ldr     r8, [r2, #GICH_ELRSR0]
        ldr     r9, [r2, #GICH_ELRSR1]
        ldr     r10, [r2, #GICH_APR]
-
-       str     r3, [r11, #VGIC_CPU_HCR]
-       str     r4, [r11, #VGIC_CPU_VMCR]
-       str     r5, [r11, #VGIC_CPU_MISR]
-       str     r6, [r11, #VGIC_CPU_EISR]
-       str     r7, [r11, #(VGIC_CPU_EISR + 4)]
-       str     r8, [r11, #VGIC_CPU_ELRSR]
-       str     r9, [r11, #(VGIC_CPU_ELRSR + 4)]
-       str     r10, [r11, #VGIC_CPU_APR]
+ARM_BE8(rev    r3, r3  )
+ARM_BE8(rev    r4, r4  )
+ARM_BE8(rev    r5, r5  )
+ARM_BE8(rev    r6, r6  )
+ARM_BE8(rev    r7, r7  )
+ARM_BE8(rev    r8, r8  )
+ARM_BE8(rev    r9, r9  )
+ARM_BE8(rev    r10, r10        )
+
+       str     r3, [r11, #VGIC_V2_CPU_HCR]
+       str     r4, [r11, #VGIC_V2_CPU_VMCR]
+       str     r5, [r11, #VGIC_V2_CPU_MISR]
+       str     r6, [r11, #VGIC_V2_CPU_EISR]
+       str     r7, [r11, #(VGIC_V2_CPU_EISR + 4)]
+       str     r8, [r11, #VGIC_V2_CPU_ELRSR]
+       str     r9, [r11, #(VGIC_V2_CPU_ELRSR + 4)]
+       str     r10, [r11, #VGIC_V2_CPU_APR]
 
        /* Clear GICH_HCR */
        mov     r5, #0
@@ -436,9 +445,10 @@ vcpu       .req    r0              @ vcpu pointer always in r0
 
        /* Save list registers */
        add     r2, r2, #GICH_LR0
-       add     r3, r11, #VGIC_CPU_LR
+       add     r3, r11, #VGIC_V2_CPU_LR
        ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:     ldr     r6, [r2], #4
+ARM_BE8(rev    r6, r6  )
        str     r6, [r3], #4
        subs    r4, r4, #1
        bne     1b
@@ -463,9 +473,12 @@ vcpu       .req    r0              @ vcpu pointer always in r0
        add     r11, vcpu, #VCPU_VGIC_CPU
 
        /* We only restore a minimal set of registers */
-       ldr     r3, [r11, #VGIC_CPU_HCR]
-       ldr     r4, [r11, #VGIC_CPU_VMCR]
-       ldr     r8, [r11, #VGIC_CPU_APR]
+       ldr     r3, [r11, #VGIC_V2_CPU_HCR]
+       ldr     r4, [r11, #VGIC_V2_CPU_VMCR]
+       ldr     r8, [r11, #VGIC_V2_CPU_APR]
+ARM_BE8(rev    r3, r3  )
+ARM_BE8(rev    r4, r4  )
+ARM_BE8(rev    r8, r8  )
 
        str     r3, [r2, #GICH_HCR]
        str     r4, [r2, #GICH_VMCR]
@@ -473,9 +486,10 @@ vcpu       .req    r0              @ vcpu pointer always in r0
 
        /* Restore list registers */
        add     r2, r2, #GICH_LR0
-       add     r3, r11, #VGIC_CPU_LR
+       add     r3, r11, #VGIC_V2_CPU_LR
        ldr     r4, [r11, #VGIC_CPU_NR_LR]
 1:     ldr     r6, [r3], #4
+ARM_BE8(rev    r6, r6  )
        str     r6, [r2], #4
        subs    r4, r4, #1
        bne     1b
@@ -506,7 +520,7 @@ vcpu        .req    r0              @ vcpu pointer always in r0
        mcr     p15, 0, r2, c14, c3, 1  @ CNTV_CTL
        isb
 
-       mrrc    p15, 3, r2, r3, c14     @ CNTV_CVAL
+       mrrc    p15, 3, rr_lo_hi(r2, r3), c14   @ CNTV_CVAL
        ldr     r4, =VCPU_TIMER_CNTV_CVAL
        add     r5, vcpu, r4
        strd    r2, r3, [r5]
@@ -546,12 +560,12 @@ vcpu      .req    r0              @ vcpu pointer always in r0
 
        ldr     r2, [r4, #KVM_TIMER_CNTVOFF]
        ldr     r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
-       mcrr    p15, 4, r2, r3, c14     @ CNTVOFF
+       mcrr    p15, 4, rr_lo_hi(r2, r3), c14   @ CNTVOFF
 
        ldr     r4, =VCPU_TIMER_CNTV_CVAL
        add     r5, vcpu, r4
        ldrd    r2, r3, [r5]
-       mcrr    p15, 3, r2, r3, c14     @ CNTV_CVAL
+       mcrr    p15, 3, rr_lo_hi(r2, r3), c14   @ CNTV_CVAL
        isb
 
        ldr     r2, [vcpu, #VCPU_TIMER_CNTV_CTL]