Merge tag 'mvebu-dt-3.17-2' of git://git.infradead.org/linux-mvebu into next/dt

[cascardo/linux.git] / arch / arm / mach-imx / pm-imx5.c

diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 58aeaf5..f1f80ab 100644 (file)
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -19,9 +19,26 @@
 
 #include "common.h"
 #include "cpuidle.h"
-#include "crm-regs-imx5.h"
 #include "hardware.h"
 
+#define MXC_CCM_CLPCR                  0x54
+#define MXC_CCM_CLPCR_LPM_OFFSET       0
+#define MXC_CCM_CLPCR_LPM_MASK         0x3
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET        9
+#define MXC_CCM_CLPCR_VSTBY            (0x1 << 8)
+#define MXC_CCM_CLPCR_SBYOS            (0x1 << 6)
+
+#define MXC_CORTEXA8_PLAT_LPC          0xc
+#define MXC_CORTEXA8_PLAT_LPC_DSM      (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM  (1 << 1)
+
+#define MXC_SRPG_NEON_SRPGCR           0x280
+#define MXC_SRPG_ARM_SRPGCR            0x2a0
+#define MXC_SRPG_EMPGC0_SRPGCR         0x2c0
+#define MXC_SRPG_EMPGC1_SRPGCR         0x2d0
+
+#define MXC_SRPGCR_PCR                 1
+
 /*
  * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
  * This is also the lowest power state possible without affecting
@@ -32,6 +49,30 @@
  */
 #define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
 
+struct imx5_pm_data {
+       phys_addr_t cortex_addr;
+       phys_addr_t gpc_addr;
+};
+
+static const struct imx5_pm_data imx51_pm_data __initconst = {
+       .cortex_addr = 0x83fa0000,
+       .gpc_addr = 0x73fd8000,
+};
+
+static const struct imx5_pm_data imx53_pm_data __initconst = {
+       .cortex_addr = 0x63fa0000,
+       .gpc_addr = 0x53fd8000,
+};
+
+static void __iomem *ccm_base;
+static void __iomem *cortex_base;
+static void __iomem *gpc_base;
+
+void __init imx5_pm_set_ccm_base(void __iomem *base)
+{
+       ccm_base = base;
+}
+
 /*
  * set cpu low power mode before WFI instruction. This function is called
  * mx5 because it can be used for mx51, and mx53.
@@ -43,12 +84,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
        int stop_mode = 0;
 
        /* always allow platform to issue a deep sleep mode request */
-       plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
+       plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
            ~(MXC_CORTEXA8_PLAT_LPC_DSM);
-       ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
-       arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
-       empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
-       empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
+       ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
+                   ~(MXC_CCM_CLPCR_LPM_MASK);
+       arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
+                    ~(MXC_SRPGCR_PCR);
+       empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
+                ~(MXC_SRPGCR_PCR);
+       empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
+                ~(MXC_SRPGCR_PCR);
 
        switch (mode) {
        case WAIT_CLOCKED:
@@ -82,17 +127,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                return;
        }
 
-       __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
-       __raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
-       __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
-       __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
+       __raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
+       __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
+       __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
+       __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
 
        if (stop_mode) {
                empgc0 |= MXC_SRPGCR_PCR;
                empgc1 |= MXC_SRPGCR_PCR;
 
-               __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
-               __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
+               __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+               __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
        }
 }
 
@@ -114,8 +159,8 @@ static int mx5_suspend_enter(suspend_state_t state)
                flush_cache_all();
 
                /*clear the EMPGC0/1 bits */
-               __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
-               __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+               __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
+               __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
        }
        cpu_do_idle();
 
@@ -149,7 +194,7 @@ static void imx5_pm_idle(void)
        imx5_cpu_do_idle();
 }
 
-static int __init imx5_pm_common_init(void)
+static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
 {
        int ret;
        struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
@@ -163,15 +208,28 @@ static int __init imx5_pm_common_init(void)
 
        arm_pm_idle = imx5_pm_idle;
 
+       cortex_base = ioremap(data->cortex_addr, SZ_16K);
+       gpc_base = ioremap(data->gpc_addr, SZ_16K);
+       WARN_ON(!ccm_base || !cortex_base || !gpc_base);
+
        /* Set the registers to the default cpu idle state. */
        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
 
-       return imx5_cpuidle_init();
+       ret = imx5_cpuidle_init();
+       if (ret)
+               pr_warn("%s: cpuidle init failed %d\n", __func__, ret);
+
+       suspend_set_ops(&mx5_suspend_ops);
+
+       return 0;
+}
+
+void __init imx51_pm_init(void)
+{
+       imx5_pm_common_init(&imx51_pm_data);
 }
 
-void __init imx5_pm_init(void)
+void __init imx53_pm_init(void)
 {
-       int ret = imx5_pm_common_init();
-       if (!ret)
-               suspend_set_ops(&mx5_suspend_ops);
+       imx5_pm_common_init(&imx53_pm_data);
 }