Merge tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...

[cascardo/linux.git] / arch / arm / mach-imx / system.c

diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 5e3027d..d14c33f 100644 (file)
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -42,7 +42,10 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
 {
        unsigned int wcr_enable;
 
-       if (wdog_clk)
+       if (!wdog_base)
+               goto reset_fallback;
+
+       if (!IS_ERR(wdog_clk))
                clk_enable(wdog_clk);
 
        if (cpu_is_mx1())
@@ -70,6 +73,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
        /* delay to allow the serial port to show the message */
        mdelay(50);
 
+reset_fallback:
        /* we'll take a jump through zero as a poor second */
        soft_restart(0);
 }
@@ -79,13 +83,10 @@ void __init mxc_arch_reset_init(void __iomem *base)
        wdog_base = base;
 
        wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
-       if (IS_ERR(wdog_clk)) {
+       if (IS_ERR(wdog_clk))
                pr_warn("%s: failed to get wdog clock\n", __func__);
-               wdog_clk = NULL;
-               return;
-       }
-
-       clk_prepare(wdog_clk);
+       else
+               clk_prepare(wdog_clk);
 }
 
 void __init mxc_arch_reset_init_dt(void)
@@ -97,13 +98,10 @@ void __init mxc_arch_reset_init_dt(void)
        WARN_ON(!wdog_base);
 
        wdog_clk = of_clk_get(np, 0);
-       if (IS_ERR(wdog_clk)) {
+       if (IS_ERR(wdog_clk))
                pr_warn("%s: failed to get wdog clock\n", __func__);
-               wdog_clk = NULL;
-               return;
-       }
-
-       clk_prepare(wdog_clk);
+       else
+               clk_prepare(wdog_clk);
 }
 
 #ifdef CONFIG_CACHE_L2X0
@@ -124,7 +122,7 @@ void __init imx_init_l2cache(void)
        }
 
        /* Configure the L2 PREFETCH and POWER registers */
-       val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+       val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
        val |= 0x70800000;
        /*
         * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
@@ -137,14 +135,12 @@ void __init imx_init_l2cache(void)
         */
        if (cpu_is_imx6q())
                val &= ~(1 << 30 | 1 << 23);
-       writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
-       val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-       writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+       writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
 
        iounmap(l2x0_base);
        of_node_put(np);
 
 out:
-       l2x0_of_init(0, ~0UL);
+       l2x0_of_init(0, ~0);
 }
 #endif