Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf

[cascardo/linux.git] / arch / arm / mach-mv78xx0 / irq.c

diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 3207344..788569e 100644 (file)
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -11,9 +11,10 @@
 #include <linux/kernel.h>
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <mach/bridge-regs.h>
+#include <asm/exception.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
+#include "bridge-regs.h"
 #include "common.h"
 
 static int __initdata gpio0_irqs[4] = {
@@ -23,12 +24,44 @@ static int __initdata gpio0_irqs[4] = {
        IRQ_MV78XX0_GPIO_24_31,
 };
 
+static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE;
+
+static asmlinkage void
+__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs)
+{
+       u32 stat;
+
+       stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF);
+       stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF);
+       if (stat) {
+               unsigned int hwirq = __fls(stat);
+               handle_IRQ(hwirq, regs);
+               return;
+       }
+       stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF);
+       stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF);
+       if (stat) {
+               unsigned int hwirq = 32 + __fls(stat);
+               handle_IRQ(hwirq, regs);
+               return;
+       }
+       stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF);
+       stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF);
+       if (stat) {
+               unsigned int hwirq = 64 + __fls(stat);
+               handle_IRQ(hwirq, regs);
+               return;
+       }
+}
+
 void __init mv78xx0_init_irq(void)
 {
        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
        orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
 
+       set_handle_irq(mv78xx0_legacy_handle_irq);
+
        /*
         * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
         * registers for core #1 are at an offset of 0x18 from those of