Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm

[cascardo/linux.git] / arch / arm / mach-omap2 / omap-smp.c

diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 596eb70..9a35adf 100644 (file)
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,11 +26,19 @@
 
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
 
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
 
+#define CPU_MASK               0xff0ffff0
+#define CPU_CORTEX_A9          0x410FC090
+#define CPU_CORTEX_A15         0x410FC0F0
+
+#define OMAP5_CORE_COUNT       0x2
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -73,6 +81,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        static struct clockdomain *cpu1_clkdm;
        static bool booted;
+       void __iomem *base = omap_get_wakeupgen_base();
+
        /*
         * Set synchronisation state between this boot processor
         * and the secondary one
@@ -85,7 +95,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         * the AuxCoreBoot1 register is updated with cpu state
         * A barrier is added to ensure that write buffer is drained
         */
-       omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+       if (omap_secure_apis_support())
+               omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+       else
+               __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
        flush_cache_all();
        smp_wmb();
 
@@ -124,13 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
+       void __iomem *base = omap_get_wakeupgen_base();
        /*
         * Write the address of secondary startup routine into the
         * AuxCoreBoot1 where ROM code will jump and start executing
         * on secondary core once out of WFE
         * A barrier is added to ensure that write buffer is drained
         */
-       omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+       if (omap_secure_apis_support())
+               omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+       else
+               __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                               base + OMAP_AUX_CORE_BOOT_1);
+
        smp_wmb();
 
        /*
@@ -147,16 +167,21 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-       unsigned int i, ncores;
-
-       /*
-        * Currently we can't call ioremap here because
-        * SoC detection won't work until after init_early.
-        */
-       scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
-       BUG_ON(!scu_base);
-
-       ncores = scu_get_core_count(scu_base);
+       unsigned int i = 0, ncores = 1, cpu_id;
+
+       /* Use ARM cpuid check here, as SoC detection will not work so early */
+       cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+       if (cpu_id == CPU_CORTEX_A9) {
+               /*
+                * Currently we can't call ioremap here because
+                * SoC detection won't work until after init_early.
+                */
+               scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+               BUG_ON(!scu_base);
+               ncores = scu_get_core_count(scu_base);
+       } else if (cpu_id == CPU_CORTEX_A15) {
+               ncores = OMAP5_CORE_COUNT;
+       }
 
        /* sanity check */
        if (ncores > nr_cpu_ids) {
@@ -178,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         * Initialise the SCU and wake up the secondary core using
         * wakeup_secondary().
         */
-       scu_enable(scu_base);
+       if (scu_base)
+               scu_enable(scu_base);
        wakeup_secondary();
 }