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Merge branch 'samsung/cleanup' into samsung/driver
[cascardo/linux.git] / arch / arm / mach-s5p64x0 / clock-s5p6440.c
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d..4b3023e 100644 (file)
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -31,7 +31,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5p6440.h>
+
+#include "common.h"
 
 static u32 epll_div[][5] = {
        { 36000000,     0,      48, 1, 4 },
@@ -267,18 +268,6 @@ static struct clk init_clocks_off[] = {
                .parent         = &clk_pclk.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 31),
-       }, {
-               .name           = "sclk_spi_48",
-               .devname        = "s3c64xx-spi.0",
-               .parent         = &clk_48m,
-               .enable         = s5p64x0_sclk_ctrl,
-               .ctrlbit        = (1 << 22),
-       }, {
-               .name           = "sclk_spi_48",
-               .devname        = "s3c64xx-spi.1",
-               .parent         = &clk_48m,
-               .enable         = s5p64x0_sclk_ctrl,
-               .ctrlbit        = (1 << 23),
        }, {
                .name           = "mmc_48m",
                .devname        = "s3c-sdhci.0",
@@ -390,65 +379,6 @@ static struct clksrc_sources clkset_audio = {
 
 static struct clksrc_clk clksrcs[] = {
        {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .ctrlbit        = (1 << 24),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group1,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .ctrlbit        = (1 << 25),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group1,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .ctrlbit        = (1 << 26),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group1,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "uclk1",
-                       .ctrlbit        = (1 << 5),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_uart,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_spi",
-                       .devname        = "s3c64xx-spi.0",
-                       .ctrlbit        = (1 << 20),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group1,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_spi",
-                       .devname        = "s3c64xx-spi.1",
-                       .ctrlbit        = (1 << 21),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group1,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-       }, {
                .clk    = {
                        .name           = "sclk_post",
                        .ctrlbit        = (1 << 10),
@@ -487,6 +417,77 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .ctrlbit        = (1 << 24),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group1,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .ctrlbit        = (1 << 25),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group1,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .ctrlbit        = (1 << 26),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group1,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_uclk = {
+       .clk    = {
+               .name           = "uclk1",
+               .ctrlbit        = (1 << 5),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_uart,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi0 = {
+       .clk    = {
+               .name           = "sclk_spi",
+               .devname        = "s3c64xx-spi.0",
+               .ctrlbit        = (1 << 20),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group1,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+       .clk    = {
+               .name           = "sclk_spi",
+               .devname        = "s3c64xx-spi.1",
+               .ctrlbit        = (1 << 21),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group1,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -505,6 +506,26 @@ static struct clk dummy_apb_pclk = {
        .id             = -1,
 };
 
+static struct clksrc_clk *clksrc_cdev[] = {
+       &clk_sclk_uclk,
+       &clk_sclk_spi0,
+       &clk_sclk_spi1,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2
+};
+
+static struct clk_lookup s5p6440_clk_lookup[] = {
+       CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
+       CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+       CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+       CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+       CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
+
 void __init_or_cpufreq s5p6440_setup_clocks(void)
 {
        struct clk *xtal_clk;
@@ -583,9 +604,12 @@ void __init s5p6440_register_clocks(void)
 
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+       for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+               s3c_register_clksrc(clksrc_cdev[ptr], 1);
 
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+       clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
 
        s3c24xx_register_clock(&dummy_apb_pclk);
 
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