Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

[cascardo/linux.git] / arch / arm / mach-tegra / pcie.c

diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 14b29ab..54a816f 100644 (file)
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -585,10 +585,10 @@ static void tegra_pcie_setup_translations(void)
        afi_writel(0, AFI_MSI_BAR_SZ);
 }
 
-static void tegra_pcie_enable_controller(void)
+static int tegra_pcie_enable_controller(void)
 {
        u32 val, reg;
-       int i;
+       int i, timeout;
 
        /* Enable slot clock and pulse the reset signals */
        for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
@@ -639,8 +639,14 @@ static void tegra_pcie_enable_controller(void)
        pads_writel(0xfa5cfa5c, 0xc8);
 
        /* Wait for the PLL to lock */
+       timeout = 300;
        do {
                val = pads_readl(PADS_PLL_CTL);
+               usleep_range(1000, 1000);
+               if (--timeout == 0) {
+                       pr_err("Tegra PCIe error: timeout waiting for PLL\n");
+                       return -EBUSY;
+               }
        } while (!(val & PADS_PLL_CTL_LOCKDET));
 
        /* turn off IDDQ override */
@@ -671,7 +677,7 @@ static void tegra_pcie_enable_controller(void)
        /* Disable all execptions */
        afi_writel(0, AFI_FPCI_ERROR_MASKS);
 
-       return;
+       return 0;
 }
 
 static void tegra_pcie_xclk_clamp(bool clamp)
@@ -921,7 +927,9 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
        if (err)
                return err;
 
-       tegra_pcie_enable_controller();
+       err = tegra_pcie_enable_controller();
+       if (err)
+               return err;
 
        /* setup the AFI address translations */
        tegra_pcie_setup_translations();