ARM: MM: Add DT binding for Feroceon L2 cache

[cascardo/linux.git] / arch / arm / mm / cache-feroceon-l2.c

diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 898362e..8dc1a2b 100644 (file)
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -13,11 +13,16 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/highmem.h>
+#include <linux/io.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
 #include <asm/hardware/cache-feroceon-l2.h>
 
+#define L2_WRITETHROUGH_KIRKWOOD       BIT(4)
+
 /*
  * Low-level cache maintenance operations.
  *
@@ -350,3 +355,41 @@ void __init feroceon_l2_init(int __l2_wt_override)
        printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
                         l2_wt_override ? ", in WT override mode" : "");
 }
+#ifdef CONFIG_OF
+static const struct of_device_id feroceon_ids[] __initconst = {
+       { .compatible = "marvell,kirkwood-cache"},
+       { .compatible = "marvell,feroceon-cache"},
+       {}
+};
+
+int __init feroceon_of_init(void)
+{
+       struct device_node *node;
+       void __iomem *base;
+       bool l2_wt_override = false;
+       struct resource res;
+
+#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
+       l2_wt_override = true;
+#endif
+
+       node = of_find_matching_node(NULL, feroceon_ids);
+       if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) {
+               if (of_address_to_resource(node, 0, &res))
+                       return -ENODEV;
+
+               base = ioremap(res.start, resource_size(&res));
+               if (!base)
+                       return -ENOMEM;
+
+               if (l2_wt_override)
+                       writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base);
+               else
+                       writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base);
+       }
+
+       feroceon_l2_init(l2_wt_override);
+
+       return 0;
+}
+#endif