Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / mm / cache-v7.S

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index b966656..a134d8a 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -36,10 +36,10 @@ ENTRY(v7_invalidate_l1)
        mcr     p15, 2, r0, c0, c0, 0
        mrc     p15, 1, r0, c0, c0, 0
 
-       ldr     r1, =0x7fff
+       movw    r1, #0x7fff
        and     r2, r1, r0, lsr #13
 
-       ldr     r1, =0x3ff
+       movw    r1, #0x3ff
 
        and     r3, r1, r0, lsr #3      @ NumWays - 1
        add     r2, r2, #1              @ NumSets
@@ -90,21 +90,20 @@ ENDPROC(v7_flush_icache_all)
 ENTRY(v7_flush_dcache_louis)
        dmb                                     @ ensure ordering with previous memory accesses
        mrc     p15, 1, r0, c0, c0, 1           @ read clidr, r0 = clidr
-       ALT_SMP(ands    r3, r0, #(7 << 21))     @ extract LoUIS from clidr
-       ALT_UP(ands     r3, r0, #(7 << 27))     @ extract LoUU from clidr
+ALT_SMP(mov    r3, r0, lsr #20)                @ move LoUIS into position
+ALT_UP(        mov     r3, r0, lsr #26)                @ move LoUU into position
+       ands    r3, r3, #7 << 1                 @ extract LoU*2 field from clidr
+       bne     start_flush_levels              @ LoU != 0, start flushing
 #ifdef CONFIG_ARM_ERRATA_643719
-       ALT_SMP(mrceq   p15, 0, r2, c0, c0, 0)  @ read main ID register
-       ALT_UP(reteq    lr)                     @ LoUU is zero, so nothing to do
-       ldreq   r1, =0x410fc090                 @ ID of ARM Cortex A9 r0p?
-       biceq   r2, r2, #0x0000000f             @ clear minor revision number
-       teqeq   r2, r1                          @ test for errata affected core and if so...
-       orreqs  r3, #(1 << 21)                  @   fix LoUIS value (and set flags state to 'ne')
+ALT_SMP(mrc    p15, 0, r2, c0, c0, 0)          @ read main ID register
+ALT_UP(        ret     lr)                             @ LoUU is zero, so nothing to do
+       movw    r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
+       movt    r1, #:upper16:(0x410fc090 >> 4)
+       teq     r1, r2, lsr #4                  @ test for errata affected core and if so...
+       moveq   r3, #1 << 1                     @   fix LoUIS value
+       beq     start_flush_levels              @   start flushing cache levels
 #endif
-       ALT_SMP(mov     r3, r3, lsr #20)        @ r3 = LoUIS * 2
-       ALT_UP(mov      r3, r3, lsr #26)        @ r3 = LoUU * 2
-       reteq   lr                              @ return if level == 0
-       mov     r10, #0                         @ r10 (starting level) = 0
-       b       flush_levels                    @ start flushing cache levels
+       ret     lr
 ENDPROC(v7_flush_dcache_louis)
 
 /*
@@ -119,9 +118,10 @@ ENDPROC(v7_flush_dcache_louis)
 ENTRY(v7_flush_dcache_all)
        dmb                                     @ ensure ordering with previous memory accesses
        mrc     p15, 1, r0, c0, c0, 1           @ read clidr
-       ands    r3, r0, #0x7000000              @ extract loc from clidr
-       mov     r3, r3, lsr #23                 @ left align loc bit field
+       mov     r3, r0, lsr #23                 @ move LoC into position
+       ands    r3, r3, #7 << 1                 @ extract LoC*2 from clidr
        beq     finished                        @ if loc is 0, then no need to clean
+start_flush_levels:
        mov     r10, #0                         @ start clean at cache level 0
 flush_levels:
        add     r2, r10, r10, lsr #1            @ work out 3x current cache level
@@ -140,10 +140,10 @@ flush_levels:
 #endif
        and     r2, r1, #7                      @ extract the length of the cache lines
        add     r2, r2, #4                      @ add 4 (line length offset)
-       ldr     r4, =0x3ff
+       movw    r4, #0x3ff
        ands    r4, r4, r1, lsr #3              @ find maximum number on the way size
        clz     r5, r4                          @ find bit position of way size increment
-       ldr     r7, =0x7fff
+       movw    r7, #0x7fff
        ands    r7, r7, r1, lsr #13             @ extract max number of the index size
 loop1:
        mov     r9, r7                          @ create working copy of max index