Merge tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git...

[cascardo/linux.git] / arch / arm / mm / cache-v7.S

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index d062f8c..a134d8a 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -93,18 +93,17 @@ ENTRY(v7_flush_dcache_louis)
 ALT_SMP(mov    r3, r0, lsr #20)                @ move LoUIS into position
 ALT_UP(        mov     r3, r0, lsr #26)                @ move LoUU into position
        ands    r3, r3, #7 << 1                 @ extract LoU*2 field from clidr
+       bne     start_flush_levels              @ LoU != 0, start flushing
 #ifdef CONFIG_ARM_ERRATA_643719
-       ALT_SMP(mrceq   p15, 0, r2, c0, c0, 0)  @ read main ID register
-       ALT_UP(reteq    lr)                     @ LoUU is zero, so nothing to do
-       movweq  r1, #:lower16:0x410fc090        @ ID of ARM Cortex A9 r0p?
-       movteq  r1, #:upper16:0x410fc090
-       biceq   r2, r2, #0x0000000f             @ clear minor revision number
-       teqeq   r2, r1                          @ test for errata affected core and if so...
-       moveqs  r3, #1 << 1                     @   fix LoUIS value (and set flags state to 'ne')
+ALT_SMP(mrc    p15, 0, r2, c0, c0, 0)          @ read main ID register
+ALT_UP(        ret     lr)                             @ LoUU is zero, so nothing to do
+       movw    r1, #:lower16:(0x410fc090 >> 4) @ ID of ARM Cortex A9 r0p?
+       movt    r1, #:upper16:(0x410fc090 >> 4)
+       teq     r1, r2, lsr #4                  @ test for errata affected core and if so...
+       moveq   r3, #1 << 1                     @   fix LoUIS value
+       beq     start_flush_levels              @   start flushing cache levels
 #endif
-       reteq   lr                              @ return if level == 0
-       mov     r10, #0                         @ r10 (starting level) = 0
-       b       flush_levels                    @ start flushing cache levels
+       ret     lr
 ENDPROC(v7_flush_dcache_louis)
 
 /*
@@ -122,6 +121,7 @@ ENTRY(v7_flush_dcache_all)
        mov     r3, r0, lsr #23                 @ move LoC into position
        ands    r3, r3, #7 << 1                 @ extract LoC*2 from clidr
        beq     finished                        @ if loc is 0, then no need to clean
+start_flush_levels:
        mov     r10, #0                         @ start clean at cache level 0
 flush_levels:
        add     r2, r10, r10, lsr #1            @ work out 3x current cache level