Merge tag 'nfs-for-4.8-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs

[cascardo/linux.git] / arch / arm64 / boot / dts / qcom / msm8996.dtsi

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 0506fb8..55ec3e8 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -151,6 +151,36 @@
                        reg = <0x300000 0x90000>;
                };
 
+               blsp1_spi0: spi@07575000 {
+                       compatible = "qcom,spi-qup-v2.2.1";
+                       reg = <0x07575000 0x600>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+                                <&gcc GCC_BLSP1_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&blsp1_spi0_default>;
+                       pinctrl-1 = <&blsp1_spi0_sleep>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               blsp2_i2c0: i2c@075b5000 {
+                       compatible = "qcom,i2c-qup-v2.2.1";
+                       reg = <0x075b5000 0x1000>;
+                       interrupts = <GIC_SPI 101 0>;
+                       clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+                               <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+                       clock-names = "iface", "core";
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&blsp2_i2c0_default>;
+                       pinctrl-1 = <&blsp2_i2c0_sleep>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                blsp2_uart1: serial@75b0000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0x75b0000 0x1000>;
@@ -161,7 +191,77 @@
                        status = "disabled";
                };
 
-               pinctrl@1010000 {
+               blsp2_i2c1: i2c@075b6000 {
+                       compatible = "qcom,i2c-qup-v2.2.1";
+                       reg = <0x075b6000 0x1000>;
+                       interrupts = <GIC_SPI 102 0>;
+                       clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+                               <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+                       clock-names = "iface", "core";
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&blsp2_i2c1_default>;
+                       pinctrl-1 = <&blsp2_i2c1_sleep>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               blsp2_uart2: serial@75b1000 {
+                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                       reg = <0x075b1000 0x1000>;
+                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
+                                <&gcc GCC_BLSP2_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       status = "disabled";
+               };
+
+               blsp1_i2c2: i2c@07577000 {
+                       compatible = "qcom,i2c-qup-v2.2.1";
+                       reg = <0x07577000 0x1000>;
+                       interrupts = <GIC_SPI 97 0>;
+                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+                               <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+                       clock-names = "iface", "core";
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&blsp1_i2c2_default>;
+                       pinctrl-1 = <&blsp1_i2c2_sleep>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               blsp2_spi5: spi@075ba000{
+                       compatible = "qcom,spi-qup-v2.2.1";
+                       reg = <0x075ba000 0x600>;
+                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
+                                <&gcc GCC_BLSP2_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       pinctrl-names = "default", "sleep";
+                       pinctrl-0 = <&blsp2_spi5_default>;
+                       pinctrl-1 = <&blsp2_spi5_sleep>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               sdhc2: sdhci@74a4900 {
+                        status = "disabled";
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+
+                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+
+                        clock-names = "iface", "core";
+                        clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+                        <&gcc GCC_SDCC2_APPS_CLK>;
+                        bus-width = <4>;
+                };
+
+               msmgpio: pinctrl@1010000 {
                        compatible = "qcom,msm8996-pinctrl";
                        reg = <0x01010000 0x300000>;
                        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -267,3 +367,4 @@
                };
        };
 };
+#include "msm8996-pins.dtsi"