Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetoot...

[cascardo/linux.git] / arch / arm64 / include / asm / kvm_arm.h

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index cc83520..8afb863 100644 (file)
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -18,6 +18,7 @@
 #ifndef __ARM64_KVM_ARM_H__
 #define __ARM64_KVM_ARM_H__
 
+#include <asm/memory.h>
 #include <asm/types.h>
 
 /* Hyp Configuration Register (HCR) bits */
@@ -122,6 +123,17 @@
 #define VTCR_EL2_T0SZ_MASK     0x3f
 #define VTCR_EL2_T0SZ_40B      24
 
+/*
+ * We configure the Stage-2 page tables to always restrict the IPA space to be
+ * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
+ * not known to exist and will break with this configuration.
+ *
+ * Note that when using 4K pages, we concatenate two first level page tables
+ * together.
+ *
+ * The magic numbers used for VTTBR_X in this patch can be found in Tables
+ * D4-23 and D4-25 in ARM DDI 0487A.b.
+ */
 #ifdef CONFIG_ARM64_64K_PAGES
 /*
  * Stage2 translation configuration:
@@ -149,9 +161,9 @@
 #endif
 
 #define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
-#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
-#define VTTBR_VMID_SHIFT  (48LLU)
-#define VTTBR_VMID_MASK          (0xffLLU << VTTBR_VMID_SHIFT)
+#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (UL(48))
+#define VTTBR_VMID_MASK          (UL(0xFF) << VTTBR_VMID_SHIFT)
 
 /* Hyp System Trap Register */
 #define HSTR_EL2_TTEE  (1 << 16)
@@ -174,13 +186,13 @@
 
 /* Exception Syndrome Register (ESR) bits */
 #define ESR_EL2_EC_SHIFT       (26)
-#define ESR_EL2_EC             (0x3fU << ESR_EL2_EC_SHIFT)
-#define ESR_EL2_IL             (1U << 25)
+#define ESR_EL2_EC             (UL(0x3f) << ESR_EL2_EC_SHIFT)
+#define ESR_EL2_IL             (UL(1) << 25)
 #define ESR_EL2_ISS            (ESR_EL2_IL - 1)
 #define ESR_EL2_ISV_SHIFT      (24)
-#define ESR_EL2_ISV            (1U << ESR_EL2_ISV_SHIFT)
+#define ESR_EL2_ISV            (UL(1) << ESR_EL2_ISV_SHIFT)
 #define ESR_EL2_SAS_SHIFT      (22)
-#define ESR_EL2_SAS            (3U << ESR_EL2_SAS_SHIFT)
+#define ESR_EL2_SAS            (UL(3) << ESR_EL2_SAS_SHIFT)
 #define ESR_EL2_SSE            (1 << 21)
 #define ESR_EL2_SRT_SHIFT      (16)
 #define ESR_EL2_SRT_MASK       (0x1f << ESR_EL2_SRT_SHIFT)
@@ -194,16 +206,16 @@
 #define ESR_EL2_FSC_TYPE       (0x3c)
 
 #define ESR_EL2_CV_SHIFT       (24)
-#define ESR_EL2_CV             (1U << ESR_EL2_CV_SHIFT)
+#define ESR_EL2_CV             (UL(1) << ESR_EL2_CV_SHIFT)
 #define ESR_EL2_COND_SHIFT     (20)
-#define ESR_EL2_COND           (0xfU << ESR_EL2_COND_SHIFT)
+#define ESR_EL2_COND           (UL(0xf) << ESR_EL2_COND_SHIFT)
 
 
 #define FSC_FAULT      (0x04)
 #define FSC_PERM       (0x0c)
 
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
-#define HPFAR_MASK     (~0xFUL)
+#define HPFAR_MASK     (~UL(0xf))
 
 #define ESR_EL2_EC_UNKNOWN     (0x00)
 #define ESR_EL2_EC_WFI         (0x01)