Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...

[cascardo/linux.git] / arch / mips / ath79 / pci.c

diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c
index 81ef579..730c0b0 100644 (file)
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -19,7 +19,6 @@
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include <asm/mach-ath79/ath79.h>
 #include <asm/mach-ath79/irq.h>
-#include <asm/mach-ath79/pci.h>
 #include "pci.h"
 
 static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
@@ -50,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
        }
 };
 
+static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
+       {
+               .bus    = 0,
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = ATH79_PCI_IRQ(0),
+       },
+       {
+               .bus    = 1,
+               .slot   = 0,
+               .pin    = 1,
+               .irq    = ATH79_PCI_IRQ(1),
+       },
+};
+
 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 {
        int irq = -1;
@@ -65,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
                           soc_is_ar9344()) {
                        ath79_pci_irq_map = ar724x_pci_irq_map;
                        ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
+               } else if (soc_is_qca955x()) {
+                       ath79_pci_irq_map = qca955x_pci_irq_map;
+                       ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
                } else {
                        pr_crit("pci %s: invalid irq map\n",
                                pci_name((struct pci_dev *) dev));
@@ -76,7 +93,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
                const struct ath79_pci_irq *entry;
 
                entry = &ath79_pci_irq_map[i];
-               if (entry->slot == slot && entry->pin == pin) {
+               if (entry->bus == dev->bus->number &&
+                   entry->slot == slot &&
+                   entry->pin == pin) {
                        irq = entry->irq;
                        break;
                }
@@ -116,7 +135,7 @@ static struct platform_device *
 ath79_register_pci_ar71xx(void)
 {
        struct platform_device *pdev;
-       struct resource res[2];
+       struct resource res[4];
 
        memset(res, 0, sizeof(res));
 
@@ -126,8 +145,18 @@ ath79_register_pci_ar71xx(void)
        res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
 
        res[1].flags = IORESOURCE_IRQ;
-       res[1].start = ATH79_CPU_IRQ_IP2;
-       res[1].end = ATH79_CPU_IRQ_IP2;
+       res[1].start = ATH79_CPU_IRQ(2);
+       res[1].end = ATH79_CPU_IRQ(2);
+
+       res[2].name = "io_base";
+       res[2].flags = IORESOURCE_IO;
+       res[2].start = 0;
+       res[2].end = 0;
+
+       res[3].name = "mem_base";
+       res[3].flags = IORESOURCE_MEM;
+       res[3].start = AR71XX_PCI_MEM_BASE;
+       res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
 
        pdev = platform_device_register_simple("ar71xx-pci", -1,
                                               res, ARRAY_SIZE(res));
@@ -138,10 +167,14 @@ static struct platform_device *
 ath79_register_pci_ar724x(int id,
                          unsigned long cfg_base,
                          unsigned long ctrl_base,
+                         unsigned long crp_base,
+                         unsigned long mem_base,
+                         unsigned long mem_size,
+                         unsigned long io_base,
                          int irq)
 {
        struct platform_device *pdev;
-       struct resource res[3];
+       struct resource res[6];
 
        memset(res, 0, sizeof(res));
 
@@ -159,6 +192,21 @@ ath79_register_pci_ar724x(int id,
        res[2].start = irq;
        res[2].end = irq;
 
+       res[3].name = "mem_base";
+       res[3].flags = IORESOURCE_MEM;
+       res[3].start = mem_base;
+       res[3].end = mem_base + mem_size - 1;
+
+       res[4].name = "io_base";
+       res[4].flags = IORESOURCE_IO;
+       res[4].start = io_base;
+       res[4].end = io_base;
+
+       res[5].name = "crp_base";
+       res[5].flags = IORESOURCE_MEM;
+       res[5].start = crp_base;
+       res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
+
        pdev = platform_device_register_simple("ar724x-pci", id,
                                               res, ARRAY_SIZE(res));
        return pdev;
@@ -174,7 +222,11 @@ int __init ath79_register_pci(void)
                pdev = ath79_register_pci_ar724x(-1,
                                                 AR724X_PCI_CFG_BASE,
                                                 AR724X_PCI_CTRL_BASE,
-                                                ATH79_CPU_IRQ_IP2);
+                                                AR724X_PCI_CRP_BASE,
+                                                AR724X_PCI_MEM_BASE,
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
+                                                ATH79_CPU_IRQ(2));
        } else if (soc_is_ar9342() ||
                   soc_is_ar9344()) {
                u32 bootstrap;
@@ -186,7 +238,29 @@ int __init ath79_register_pci(void)
                pdev = ath79_register_pci_ar724x(-1,
                                                 AR724X_PCI_CFG_BASE,
                                                 AR724X_PCI_CTRL_BASE,
+                                                AR724X_PCI_CRP_BASE,
+                                                AR724X_PCI_MEM_BASE,
+                                                AR724X_PCI_MEM_SIZE,
+                                                0,
                                                 ATH79_IP2_IRQ(0));
+       } else if (soc_is_qca9558()) {
+               pdev = ath79_register_pci_ar724x(0,
+                                                QCA955X_PCI_CFG_BASE0,
+                                                QCA955X_PCI_CTRL_BASE0,
+                                                QCA955X_PCI_CRP_BASE0,
+                                                QCA955X_PCI_MEM_BASE0,
+                                                QCA955X_PCI_MEM_SIZE,
+                                                0,
+                                                ATH79_IP2_IRQ(0));
+
+               pdev = ath79_register_pci_ar724x(1,
+                                                QCA955X_PCI_CFG_BASE1,
+                                                QCA955X_PCI_CTRL_BASE1,
+                                                QCA955X_PCI_CRP_BASE1,
+                                                QCA955X_PCI_MEM_BASE1,
+                                                QCA955X_PCI_MEM_SIZE,
+                                                1,
+                                                ATH79_IP3_IRQ(2));
        } else {
                /* No PCI support */
                return -ENODEV;