MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON

[cascardo/linux.git] / arch / mips / cavium-octeon / Kconfig

diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 227705d..6028666 100644 (file)
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -10,6 +10,17 @@ config CAVIUM_CN63XXP1
          non-CN63XXP1 hardware, so it is recommended to select "n"
          unless it is known the workarounds are needed.
 
+config CAVIUM_OCTEON_CVMSEG_SIZE
+       int "Number of L1 cache lines reserved for CVMSEG memory"
+       range 0 54
+       default 1
+       help
+         CVMSEG LM is a segment that accesses portions of the dcache as a
+         local memory; the larger CVMSEG is, the smaller the cache is.
+         This selects the size of CVMSEG LM, which is in cache blocks. The
+         legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
+         between zero and 6192 bytes).
+
 endif # CPU_CAVIUM_OCTEON
 
 if CAVIUM_OCTEON_SOC
@@ -23,17 +34,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
          with this option to be run at the same time as one built without this
          option.
 
-config CAVIUM_OCTEON_CVMSEG_SIZE
-       int "Number of L1 cache lines reserved for CVMSEG memory"
-       range 0 54
-       default 1
-       help
-         CVMSEG LM is a segment that accesses portions of the dcache as a
-         local memory; the larger CVMSEG is, the smaller the cache is.
-         This selects the size of CVMSEG LM, which is in cache blocks. The
-         legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
-         between zero and 6192 bytes).
-
 config CAVIUM_OCTEON_LOCK_L2
        bool "Lock often used kernel code in the L2"
        default "y"
@@ -86,7 +86,6 @@ config SWIOTLB
        select IOMMU_HELPER
        select NEED_SG_DMA_LENGTH
 
-
 config OCTEON_ILM
        tristate "Module to measure interrupt latency using Octeon CIU Timer"
        help