Merge branch '3.16-fixes' into mips-for-linux-next

[cascardo/linux.git] / arch / mips / include / asm / mach-au1x00 / gpio-au1000.h

diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 796afd0..9785e4e 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -25,20 +25,20 @@
 #define MAKE_IRQ(intc, off)    (AU1000_INTC##intc##_INT_BASE + (off))
 
 /* GPIO1 registers within SYS_ area */
-#define SYS_TRIOUTRD           0x100
-#define SYS_TRIOUTCLR          0x100
-#define SYS_OUTPUTRD           0x108
-#define SYS_OUTPUTSET          0x108
-#define SYS_OUTPUTCLR          0x10C
-#define SYS_PINSTATERD         0x110
-#define SYS_PININPUTEN         0x110
+#define AU1000_SYS_TRIOUTRD    0x100
+#define AU1000_SYS_TRIOUTCLR   0x100
+#define AU1000_SYS_OUTPUTRD    0x108
+#define AU1000_SYS_OUTPUTSET   0x108
+#define AU1000_SYS_OUTPUTCLR   0x10C
+#define AU1000_SYS_PINSTATERD  0x110
+#define AU1000_SYS_PININPUTEN  0x110
 
 /* register offsets within GPIO2 block */
-#define GPIO2_DIR              0x00
-#define GPIO2_OUTPUT           0x08
-#define GPIO2_PINSTATE         0x0C
-#define GPIO2_INTENABLE                0x10
-#define GPIO2_ENABLE           0x14
+#define AU1000_GPIO2_DIR       0x00
+#define AU1000_GPIO2_OUTPUT    0x08
+#define AU1000_GPIO2_PINSTATE  0x0C
+#define AU1000_GPIO2_INTENABLE 0x10
+#define AU1000_GPIO2_ENABLE    0x14
 
 struct gpio;
 
@@ -217,26 +217,21 @@ static inline int au1200_irq_to_gpio(int irq)
  */
 static inline void alchemy_gpio1_set_value(int gpio, int v)
 {
-       void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
-       unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
-       __raw_writel(mask, base + r);
-       wmb();
+       unsigned long r = v ? AU1000_SYS_OUTPUTSET : AU1000_SYS_OUTPUTCLR;
+       alchemy_wrsys(mask, r);
 }
 
 static inline int alchemy_gpio1_get_value(int gpio)
 {
-       void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
-       return __raw_readl(base + SYS_PINSTATERD) & mask;
+       return alchemy_rdsys(AU1000_SYS_PINSTATERD) & mask;
 }
 
 static inline int alchemy_gpio1_direction_input(int gpio)
 {
-       void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
-       __raw_writel(mask, base + SYS_TRIOUTCLR);
-       wmb();
+       alchemy_wrsys(mask, AU1000_SYS_TRIOUTCLR);
        return 0;
 }
 
@@ -279,13 +274,13 @@ static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
-       unsigned long d = __raw_readl(base + GPIO2_DIR);
+       unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR);
 
        if (to_out)
                d |= mask;
        else
                d &= ~mask;
-       __raw_writel(d, base + GPIO2_DIR);
+       __raw_writel(d, base + AU1000_GPIO2_DIR);
        wmb();
 }
 
@@ -294,14 +289,15 @@ static inline void alchemy_gpio2_set_value(int gpio, int v)
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
        unsigned long mask;
        mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
-       __raw_writel(mask, base + GPIO2_OUTPUT);
+       __raw_writel(mask, base + AU1000_GPIO2_OUTPUT);
        wmb();
 }
 
 static inline int alchemy_gpio2_get_value(int gpio)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-       return __raw_readl(base + GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
+       return __raw_readl(base + AU1000_GPIO2_PINSTATE) &
+                               (1 << (gpio - ALCHEMY_GPIO2_BASE));
 }
 
 static inline int alchemy_gpio2_direction_input(int gpio)
@@ -352,12 +348,12 @@ static inline int alchemy_gpio2_to_irq(int gpio)
 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-       unsigned long r = __raw_readl(base + GPIO2_INTENABLE);
+       unsigned long r = __raw_readl(base + AU1000_GPIO2_INTENABLE);
        if (en)
                r |= 1 << gpio2;
        else
                r &= ~(1 << gpio2);
-       __raw_writel(r, base + GPIO2_INTENABLE);
+       __raw_writel(r, base + AU1000_GPIO2_INTENABLE);
        wmb();
 }
 
@@ -434,9 +430,9 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
 static inline void alchemy_gpio2_enable(void)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-       __raw_writel(3, base + GPIO2_ENABLE);   /* reset, clock enabled */
+       __raw_writel(3, base + AU1000_GPIO2_ENABLE);    /* reset, clock enabled */
        wmb();
-       __raw_writel(1, base + GPIO2_ENABLE);   /* clock enabled */
+       __raw_writel(1, base + AU1000_GPIO2_ENABLE);    /* clock enabled */
        wmb();
 }
 
@@ -448,7 +444,7 @@ static inline void alchemy_gpio2_enable(void)
 static inline void alchemy_gpio2_disable(void)
 {
        void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR);
-       __raw_writel(2, base + GPIO2_ENABLE);   /* reset, clock disabled */
+       __raw_writel(2, base + AU1000_GPIO2_ENABLE);    /* reset, clock disabled */
        wmb();
 }