MIPS: pm-cps: Support CM3 changes to Coherence Enable Register

[cascardo/linux.git] / arch / mips / include / asm / mips-cm.h

diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 58e7874..2e41807 100644 (file)
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -359,6 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority,     0x80)
 /* GCR_Cx_COHERENCE register fields */
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF    0
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK    (_ULCAST_(0xff) << 0)
+#define CM3_GCR_Cx_COHERENCE_COHEN_MSK         (_ULCAST_(0x1) << 0)
 
 /* GCR_Cx_CONFIG register fields */
 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF          10
@@ -458,10 +459,21 @@ static inline int mips_cm_revision(void)
 static inline unsigned int mips_cm_max_vp_width(void)
 {
        extern int smp_num_siblings;
+       uint32_t cfg;
 
        if (mips_cm_revision() >= CM_REV_CM3)
                return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
 
+       if (mips_cm_present()) {
+               /*
+                * We presume that all cores in the system will have the same
+                * number of VP(E)s, and if that ever changes then this will
+                * need revisiting.
+                */
+               cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
+               return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
+       }
+
        if (IS_ENABLED(CONFIG_SMP))
                return smp_num_siblings;