/* clear all three cache coherency fields */
config0 &= ~(0x7 | (7<<25) | (7<<28));
- config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
- (CONF_CM_DEFAULT<<28));
+ config0 |= (_page_cachable_default >> _CACHE_SHIFT) |
+ (CONF_CM_DEFAULT << 25) | (CONF_CM_DEFAULT << 28);
write_c0_config(config0);
BARRIER;