Merge tag 'staging-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...

[cascardo/linux.git] / arch / powerpc / boot / dts / fsl / b4420si-post.dtsi

diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index d678944..86161ae 100644 (file)
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -80,33 +80,9 @@
                compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
        };
 
-       clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+       global-utilities@e1000 {
                compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
-               ranges = <0x0 0xe1000 0x1000>;
-               #address-cells = <1>;
-               #size-cells = <1>;
-
-               sysclk: sysclk {
-                       #clock-cells = <0>;
-                       compatible = "fsl,qoriq-sysclk-2.0";
-                       clock-output-names = "sysclk";
-               };
-
-               pll0: pll0@800 {
-                       #clock-cells = <1>;
-                       reg = <0x800 0x4>;
-                       compatible = "fsl,qoriq-core-pll-2.0";
-                       clocks = <&sysclk>;
-                       clock-output-names = "pll0", "pll0-div2", "pll0-div4";
-               };
-
-               pll1: pll1@820 {
-                       #clock-cells = <1>;
-                       reg = <0x820 0x4>;
-                       compatible = "fsl,qoriq-core-pll-2.0";
-                       clocks = <&sysclk>;
-                       clock-output-names = "pll1", "pll1-div2", "pll1-div4";
-               };
 
                mux0: mux0@0 {
                        #clock-cells = <0>;