#define FIRE_IOMMU_FLUSH 0x40100UL
#define FIRE_IOMMU_FLUSHINV 0x40108UL
-static void pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
+static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm)
{
struct iommu *iommu = pbm->iommu;
u32 vdma[2], dma_mask;
u64 control;
- int tsbsize;
+ int tsbsize, err;
/* No virtual-dma property on these guys, use largest size. */
vdma[0] = 0xc0000000; /* base */
*/
fire_write(iommu->iommu_flushinv, ~(u64)0);
- pci_iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
+ err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask);
+ if (err)
+ return err;
fire_write(iommu->iommu_tsbbase, __pa(iommu->page_table) | 0x7UL);
0x00000002 /* Bypass enable */ |
0x00000001 /* Translation enable */);
fire_write(iommu->iommu_control, control);
+
+ return 0;
}
/* Based at pbm->controller_regs */
fire_write(pbm->pbm_regs + FIRE_PEC_IENAB, ~(u64)0);
}
-static void pci_fire_pbm_init(struct pci_controller_info *p,
- struct device_node *dp, u32 portid)
+static int pci_fire_pbm_init(struct pci_controller_info *p,
+ struct device_node *dp, u32 portid)
{
const struct linux_prom64_registers *regs;
struct pci_pbm_info *pbm;
pci_get_pbm_props(pbm);
pci_fire_hw_init(pbm);
- pci_fire_pbm_iommu_init(pbm);
+
+ return pci_fire_pbm_iommu_init(pbm);
}
static inline int portid_compare(u32 x, u32 y)
for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
if (portid_compare(pbm->portid, portid)) {
- pci_fire_pbm_init(pbm->parent, dp, portid);
+ if (pci_fire_pbm_init(pbm->parent, dp, portid))
+ goto fatal_memory_error;
return;
}
}
*/
pci_memspace_mask = 0x7fffffffUL;
- pci_fire_pbm_init(p, dp, portid);
+ if (pci_fire_pbm_init(p, dp, portid))
+ goto fatal_memory_error;
+
return;
fatal_memory_error: