arch/tile: support newer binutils assembler shift semantics

[cascardo/linux.git] / arch / tile / kernel / head_32.S

diff --git a/arch/tile/kernel/head_32.S b/arch/tile/kernel/head_32.S
index 05b5f4d..1a39b7c 100644 (file)
--- a/arch/tile/kernel/head_32.S
+++ b/arch/tile/kernel/head_32.S
@@ -145,7 +145,7 @@ ENTRY(empty_zero_page)
        .endif
        .word HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED | \
              (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
-       .word (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
+       .word (\bits1) | (HV_CPA_TO_PFN(\cpa) << (HV_PTE_INDEX_PFN - 32))
        .endm
 
 __PAGE_ALIGNED_DATA
@@ -158,12 +158,14 @@ ENTRY(swapper_pg_dir)
         */
        .set addr, 0
        .rept (MEM_USER_INTRPT - PAGE_OFFSET) >> PGDIR_SHIFT
-       PTE addr + PAGE_OFFSET, addr, HV_PTE_READABLE | HV_PTE_WRITABLE
+       PTE addr + PAGE_OFFSET, addr, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
+                                     (1 << (HV_PTE_INDEX_WRITABLE - 32))
        .set addr, addr + PGDIR_SIZE
        .endr
 
        /* The true text VAs are mapped as VA = PA + MEM_SV_INTRPT */
-       PTE MEM_SV_INTRPT, 0, HV_PTE_READABLE | HV_PTE_EXECUTABLE
+       PTE MEM_SV_INTRPT, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
+                             (1 << (HV_PTE_INDEX_EXECUTABLE - 32))
        .org swapper_pg_dir + HV_L1_SIZE
        END(swapper_pg_dir)
 
@@ -176,6 +178,7 @@ ENTRY(swapper_pg_dir)
        __INITDATA
        .align CHIP_L2_LINE_SIZE()
 ENTRY(swapper_pgprot)
-       PTE     0, 0, HV_PTE_READABLE | HV_PTE_WRITABLE, 1
+       PTE     0, 0, (1 << (HV_PTE_INDEX_READABLE - 32)) | \
+                     (1 << (HV_PTE_INDEX_WRITABLE - 32)), 1
        .align CHIP_L2_LINE_SIZE()
        END(swapper_pgprot)