Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile

[cascardo/linux.git] / arch / tile / kernel / pci_gx.c

diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index f2bf200..a97a645 100644 (file)
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -602,13 +602,8 @@ static void fixup_read_and_payload_sizes(struct pci_controller *controller)
                            rc_dev_cap.word);
 
        /* Configure PCI Express MPS setting. */
-       list_for_each_entry(child, &root_bus->children, node) {
-               struct pci_dev *self = child->self;
-               if (!self)
-                       continue;
-
-               pcie_bus_configure_settings(child, self->pcie_mpss);
-       }
+       list_for_each_entry(child, &root_bus->children, node)
+               pcie_bus_configure_settings(child);
 
        /*
         * Set the mac_config register in trio based on the MPS/MRS of the link.
@@ -860,9 +855,15 @@ int __init pcibios_init(void)
 
 #endif
 
+               /*
+                * To save VMALLOC space, we take advantage of the fact that
+                * bit 29 in the PIO CFG address format is reserved 0. With
+                * TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT being 30,
+                * this cuts VMALLOC space usage from 1GB to 512MB per mac.
+                */
                trio_context->mmio_base_pio_cfg[mac] =
-                       iorpc_ioremap(trio_context->fd, offset,
-                       (1 << TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT));
+                       iorpc_ioremap(trio_context->fd, offset, (1UL <<
+                       (TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT - 1)));
                if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
                        pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
                                mac, trio_index);
@@ -1054,7 +1055,7 @@ void pcibios_fixup_bus(struct pci_bus *bus)
 }
 
 /* Process any "pci=" kernel boot arguments. */
-char *pcibios_setup(char *str)
+char *__init pcibios_setup(char *str)
 {
        if (!strcmp(str, "off")) {
                pci_probe = 0;
@@ -1075,13 +1076,24 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
        return pci_enable_resources(dev, mask);
 }
 
-/* Called for each device after PCI setup is done. */
+/*
+ * Called for each device after PCI setup is done.
+ * We initialize the PCI device capabilities conservatively, assuming that
+ * all devices can only address the 32-bit DMA space. The exception here is
+ * that the device dma_offset is set to the value that matches the 64-bit
+ * capable devices. This is OK because dma_offset is not used by legacy
+ * dma_ops, nor by the hybrid dma_ops's streaming DMAs, which are 64-bit ops.
+ * This implementation matches the kernel design of setting PCI devices'
+ * coherent_dma_mask to 0xffffffffull by default, allowing the device drivers
+ * to skip calling pci_set_consistent_dma_mask(DMA_BIT_MASK(32)).
+ */
 static void pcibios_fixup_final(struct pci_dev *pdev)
 {
-       set_dma_ops(&pdev->dev, gx_pci_dma_map_ops);
+       set_dma_ops(&pdev->dev, gx_legacy_pci_dma_map_ops);
        set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
        pdev->dev.archdata.max_direct_dma_addr =
                TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
+       pdev->dev.coherent_dma_mask = TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);