Merge tag 'samsung-cleanup-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene...

[cascardo/linux.git] / arch / x86 / kernel / quirks.c

diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 04ee1e2..7c6acd4 100644 (file)
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -571,3 +571,40 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F5,
                        quirk_amd_nb_node);
 
 #endif
+
+#ifdef CONFIG_PCI
+/*
+ * Processor does not ensure DRAM scrub read/write sequence
+ * is atomic wrt accesses to CC6 save state area. Therefore
+ * if a concurrent scrub read/write access is to same address
+ * the entry may appear as if it is not written. This quirk
+ * applies to Fam16h models 00h-0Fh
+ *
+ * See "Revision Guide" for AMD F16h models 00h-0fh,
+ * document 51810 rev. 3.04, Nov 2013
+ */
+static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
+{
+       u32 val;
+
+       /*
+        * Suggested workaround:
+        * set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
+        */
+       pci_read_config_dword(dev, 0x58, &val);
+       if (val & 0x1F) {
+               val &= ~(0x1F);
+               pci_write_config_dword(dev, 0x58, val);
+       }
+
+       pci_read_config_dword(dev, 0x5C, &val);
+       if (val & BIT(0)) {
+               val &= ~BIT(0);
+               pci_write_config_dword(dev, 0x5c, val);
+       }
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
+                       amd_disable_seq_and_redirect_scrub);
+
+#endif