drm/i915: Add support for the G33, Q33, and Q35 chipsets.

[cascardo/linux.git] / drivers / char / drm / i915_dma.c

diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c
index 730dfee..ea52740 100644 (file)
--- a/drivers/char/drm/i915_dma.c
+++ b/drivers/char/drm/i915_dma.c
@@ -38,6 +38,10 @@
                       dev->pci_device == 0x2A02 || \
                       dev->pci_device == 0x2A12)
 
+#define IS_G33(dev) (dev->pci_device == 0x29b2 || \
+                    dev->pci_device == 0x29c2 || \
+                    dev->pci_device == 0x29d2)
+
 /* Really want an OS-independent resettable timer.  Would like to have
  * this loop run for (eg) 3 sec, but have the timer reset every time
  * the head pointer changes, so that EBUSY only happens if the ring
@@ -107,6 +111,12 @@ static int i915_dma_cleanup(drm_device_t * dev)
                        I915_WRITE(0x02080, 0x1ffff000);
                }
 
+               if (dev_priv->status_gfx_addr) {
+                       dev_priv->status_gfx_addr = 0;
+                       drm_core_ioremapfree(&dev_priv->hws_map, dev);
+                       I915_WRITE(0x2080, 0x1ffff000);
+               }
+
                drm_free(dev->dev_private, sizeof(drm_i915_private_t),
                         DRM_MEM_DRIVER);
 
@@ -180,26 +190,24 @@ static int i915_initialize(drm_device_t * dev,
        dev_priv->allow_batchbuffer = 1;
 
        /* Program Hardware Status Page */
-       dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
-                                                  0xffffffff);
+       if (!IS_G33(dev)) {
+               dev_priv->status_page_dmah =
+                       drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
+
+               if (!dev_priv->status_page_dmah) {
+                       dev->dev_private = (void *)dev_priv;
+                       i915_dma_cleanup(dev);
+                       DRM_ERROR("Can not allocate hardware status page\n");
+                       return DRM_ERR(ENOMEM);
+               }
+               dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
+               dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 
-       if (!dev_priv->status_page_dmah) {
-               dev->dev_private = (void *)dev_priv;
-               i915_dma_cleanup(dev);
-               DRM_ERROR("Can not allocate hardware status page\n");
-               return DRM_ERR(ENOMEM);
+               memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+               I915_WRITE(0x02080, dev_priv->dma_status_page);
        }
-       dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
-       dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
-
-       memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
-       DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
-
-       I915_WRITE(0x02080, dev_priv->dma_status_page);
        DRM_DEBUG("Enabled hardware status page\n");
-
        dev->dev_private = (void *)dev_priv;
-
        return 0;
 }
 
@@ -232,7 +240,10 @@ static int i915_dma_resume(drm_device_t * dev)
        }
        DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 
-       I915_WRITE(0x02080, dev_priv->dma_status_page);
+       if (dev_priv->status_gfx_addr != 0)
+               I915_WRITE(0x02080, dev_priv->status_gfx_addr);
+       else
+               I915_WRITE(0x02080, dev_priv->dma_status_page);
        DRM_DEBUG("Enabled hardware status page\n");
 
        return 0;
@@ -740,6 +751,47 @@ static int i915_setparam(DRM_IOCTL_ARGS)
        return 0;
 }
 
+static int i915_set_status_page(DRM_IOCTL_ARGS)
+{
+       DRM_DEVICE;
+       drm_i915_private_t *dev_priv = dev->dev_private;
+       drm_i915_hws_addr_t hws;
+
+       if (!dev_priv) {
+               DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
+               return DRM_ERR(EINVAL);
+       }
+       DRM_COPY_FROM_USER_IOCTL(hws, (drm_i915_hws_addr_t __user *) data,
+                       sizeof(hws));
+       printk(KERN_DEBUG "set status page addr 0x%08x\n", (u32)hws.addr);
+
+       dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
+
+       dev_priv->hws_map.offset = dev->agp->agp_info.aper_base + hws.addr;
+       dev_priv->hws_map.size = 4*1024;
+       dev_priv->hws_map.type = 0;
+       dev_priv->hws_map.flags = 0;
+       dev_priv->hws_map.mtrr = 0;
+
+       drm_core_ioremap(&dev_priv->hws_map, dev);
+       if (dev_priv->hws_map.handle == NULL) {
+               dev->dev_private = (void *)dev_priv;
+               i915_dma_cleanup(dev);
+               dev_priv->status_gfx_addr = 0;
+               DRM_ERROR("can not ioremap virtual address for"
+                               " G33 hw status page\n");
+               return DRM_ERR(ENOMEM);
+       }
+       dev_priv->hw_status_page = dev_priv->hws_map.handle;
+
+       memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+       I915_WRITE(0x02080, dev_priv->status_gfx_addr);
+       DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
+                       dev_priv->status_gfx_addr);
+       DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
+       return 0;
+}
+
 int i915_driver_load(drm_device_t *dev, unsigned long flags)
 {
        /* i915 has 4 more counters */
@@ -786,6 +838,7 @@ drm_ioctl_desc_t i915_ioctls[] = {
        [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
        [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
        [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] = {i915_vblank_swap, DRM_AUTH},
+       [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] = {i915_set_status_page, DRM_AUTH},
 };
 
 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);