clk: at91: Migrate to clk_hw based registration and OF APIs

[cascardo/linux.git] / drivers / clk / at91 / clk-plldiv.c

diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index 2bed264..b4afaf2 100644 (file)
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -75,13 +75,14 @@ static const struct clk_ops plldiv_ops = {
        .set_rate = clk_plldiv_set_rate,
 };
 
-static struct clk * __init
+static struct clk_hw * __init
 at91_clk_register_plldiv(struct regmap *regmap, const char *name,
                         const char *parent_name)
 {
        struct clk_plldiv *plldiv;
-       struct clk *clk = NULL;
+       struct clk_hw *hw;
        struct clk_init_data init;
+       int ret;
 
        plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
        if (!plldiv)
@@ -96,18 +97,20 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name,
        plldiv->hw.init = &init;
        plldiv->regmap = regmap;
 
-       clk = clk_register(NULL, &plldiv->hw);
-
-       if (IS_ERR(clk))
+       hw = &plldiv->hw;
+       ret = clk_hw_register(NULL, &plldiv->hw);
+       if (ret) {
                kfree(plldiv);
+               hw = ERR_PTR(ret);
+       }
 
-       return clk;
+       return hw;
 }
 
 static void __init
 of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
 {
-       struct clk *clk;
+       struct clk_hw *hw;
        const char *parent_name;
        const char *name = np->name;
        struct regmap *regmap;
@@ -120,12 +123,11 @@ of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
        if (IS_ERR(regmap))
                return;
 
-       clk = at91_clk_register_plldiv(regmap, name, parent_name);
-       if (IS_ERR(clk))
+       hw = at91_clk_register_plldiv(regmap, name, parent_name);
+       if (IS_ERR(hw))
                return;
 
-       of_clk_add_provider(np, of_clk_src_simple_get, clk);
-       return;
+       of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 }
 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
               of_at91sam9x5_clk_plldiv_setup);