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Merge tag 'clk-v4.9-samsung' of git://linuxtv.org/snawrocki/samsung into clk-next
[cascardo/linux.git] / drivers / clk / imx / clk-imx7d.c
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 6ed4f8f..e7c7353 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -22,43 +22,63 @@
 
 #include "clk.h"
 
+static u32 share_count_sai1;
+static u32 share_count_sai2;
+static u32 share_count_sai3;
+
+static struct clk_div_table test_div_table[] = {
+       { .val = 3, .div = 1, },
+       { .val = 2, .div = 1, },
+       { .val = 1, .div = 2, },
+       { .val = 0, .div = 4, },
+       { }
+};
+
+static struct clk_div_table post_div_table[] = {
+       { .val = 3, .div = 4, },
+       { .val = 2, .div = 1, },
+       { .val = 1, .div = 2, },
+       { .val = 0, .div = 1, },
+       { }
+};
+
 static struct clk *clks[IMX7D_CLK_END];
 static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
        "pll_enet_500m_clk", "pll_dram_main_clk",
-       "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_main_clk",
+       "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
        "pll_usb_main_clk", };
 
 static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
        "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
-       "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_usb_main_clk", };
 
 static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk",
-       "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_usb_main_clk", };
 
 static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
        "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_sys_pfd7_clk", };
+       "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };
 
 static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
        "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
-       "pll_sys_pfd7_clk", "pll_audio_main_clk", "pll_video_main_clk", };
+       "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", };
 
 static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
        "pll_dram_533m_clk", "pll_enet_250m_clk",
-       "pll_sys_main_240m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_sys_pfd4_clk", };
 
 static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
        "pll_dram_533m_clk", "pll_sys_main_240m_clk",
        "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
-       "pll_audio_main_clk", };
+       "pll_audio_post_div", };
 
 static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
        "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
-       "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk",
+       "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
        "pll_video_main_clk", };
 
 static const char *dram_phym_sel[] = { "pll_dram_main_clk",
@@ -69,13 +89,13 @@ static const char *dram_sel[] = { "pll_dram_main_clk",
 
 static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
        "pll_sys_main_clk", "pll_enet_500m_clk",
-       "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_main_clk",
+       "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
        "pll_video_main_clk", };
 
 static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
        "pll_sys_main_clk", "pll_enet_500m_clk",
        "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk",
-       "pll_audio_main_clk", "pll_sys_pfd2_270m_clk", };
+       "pll_audio_post_div", "pll_sys_pfd2_270m_clk", };
 
 static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
        "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
@@ -101,53 +121,53 @@ static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
 
 static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
        "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
-       "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", };
+       "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
 
 static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
        "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
-       "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", };
+       "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", };
 
 static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
        "pll_video_main_clk", "ext_clk_3", };
 
 static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-       "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk",
+       "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
        "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
 
 static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-       "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk",
+       "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
        "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
 
 static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-       "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk",
+       "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
        "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
 
 static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
-       "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk",
+       "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk",
        "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
 
 static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
        "pll_enet_50m_clk", "pll_enet_25m_clk",
-       "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "ext_clk_4", };
 
 static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3",
+       "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
        "ext_clk_4", "pll_video_main_clk", };
 
 static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
        "pll_enet_50m_clk", "pll_enet_25m_clk",
-       "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "ext_clk_4", };
 
 static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3",
+       "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
        "ext_clk_4", "pll_video_main_clk", };
 
 static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
        "pll_enet_50m_clk", "pll_enet_125m_clk",
-       "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_sys_pfd3_clk", };
 
 static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -188,22 +208,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
 
 static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_enet_50m_clk", "pll_dram_533m_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk",
+       "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
        "pll_sys_pfd2_135m_clk", };
 
 static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_enet_50m_clk", "pll_dram_533m_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk",
+       "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
        "pll_sys_pfd2_135m_clk", };
 
 static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_enet_50m_clk", "pll_dram_533m_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk",
+       "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
        "pll_sys_pfd2_135m_clk", };
 
 static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
        "pll_enet_50m_clk", "pll_dram_533m_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk",
+       "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk",
        "pll_sys_pfd2_135m_clk", };
 
 static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
@@ -262,32 +282,32 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
        "pll_usb_main_clk", };
 
 static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
-       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk",
+       "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
        "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", };
 
 static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
        "pll_sys_main_120m_clk", "pll_dram_533m_clk",
-       "pll_usb_main_clk", "pll_audio_main_clk", "pll_enet_125m_clk",
+       "pll_usb_main_clk", "pll_audio_post_div", "pll_enet_125m_clk",
        "pll_sys_pfd7_clk", };
 
 static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
@@ -297,19 +317,19 @@ static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 
 static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
        "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
-       "ref_1m_clk", "pll_audio_main_clk", "ext_clk_1", };
+       "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
 
 static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
        "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
-       "ref_1m_clk", "pll_audio_main_clk", "ext_clk_2", };
+       "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
 
 static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
        "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
-       "ref_1m_clk", "pll_audio_main_clk", "ext_clk_3", };
+       "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
 
 static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
        "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk",
-       "ref_1m_clk", "pll_audio_main_clk", "ext_clk_4", };
+       "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
 
 static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
        "pll_sys_main_120m_clk", "pll_dram_533m_clk",
@@ -323,12 +343,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
 
 static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
        "pll_sys_main_120m_clk", "pll_dram_533m_clk",
-       "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_usb_main_clk", };
 
 static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
        "pll_sys_main_120m_clk", "pll_dram_533m_clk",
-       "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk",
+       "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk",
        "pll_usb_main_clk", };
 
 static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
@@ -342,13 +362,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
 
 static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
        "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "ckil", };
+       "pll_audio_post_div", "pll_video_main_clk", "ckil", };
 
 static const char *lvds1_sel[] = { "pll_arm_main_clk",
        "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
        "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
        "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
-       "pll_audio_main_clk", "pll_video_main_clk", "pll_enet_500m_clk",
+       "pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk",
        "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
        "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
        "pll_dram_main_clk", };
@@ -430,6 +450,11 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
        clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
 
+       clks[IMX7D_PLL_AUDIO_TEST_DIV]  = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
+                               CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
+       clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
+                               CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
+
        clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
        clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
        clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2);
@@ -779,6 +804,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
        clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
        clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
+       clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
        clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
        clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
        clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
@@ -786,9 +812,12 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
        clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
        clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
-       clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate4("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0);
-       clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate4("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0);
-       clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate4("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0);
+       clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
+       clks[IMX7D_SAI1_IPG_CLK]  = imx_clk_gate2_shared2("sai1_ipg_clk",  "ipg_root_clk",  base + 0x48c0, 0, &share_count_sai1);
+       clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
+       clks[IMX7D_SAI2_IPG_CLK]  = imx_clk_gate2_shared2("sai2_ipg_clk",  "ipg_root_clk",  base + 0x48d0, 0, &share_count_sai2);
+       clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
+       clks[IMX7D_SAI3_IPG_CLK]  = imx_clk_gate2_shared2("sai3_ipg_clk",  "ipg_root_clk",  base + 0x48e0, 0, &share_count_sai3);
        clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
        clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
        clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
@@ -860,8 +889,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
        /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
        clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
-       clk_set_parent(clks[IMX7D_ENET_AXI_ROOT_SRC], clks[IMX7D_PLL_ENET_MAIN_250M_CLK]);
-
        /* set uart module clock's parent clock source that must be great then 80MHz */
        clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
 
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