clk: rockchip: release io resource when failing to init clk

[cascardo/linux.git] / drivers / clk / rockchip / clk-rk3228.c

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 7702d28..016bdb0 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -111,7 +111,10 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
        .core_reg = RK2928_CLKSEL_CON(0),
        .div_core_shift = 0,
        .div_core_mask = 0x1f,
+       .mux_core_alt = 1,
+       .mux_core_main = 0,
        .mux_core_shift = 6,
+       .mux_core_mask = 0x1,
 };
 
 PNAME(mux_pll_p)               = { "clk_24m", "xin24m" };
@@ -625,6 +628,7 @@ static const char *const rk3228_critical_clocks[] __initconst = {
 
 static void __init rk3228_clk_init(struct device_node *np)
 {
+       struct rockchip_clk_provider *ctx;
        void __iomem *reg_base;
 
        reg_base = of_iomap(np, 0);
@@ -633,17 +637,22 @@ static void __init rk3228_clk_init(struct device_node *np)
                return;
        }
 
-       rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+       ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+       if (IS_ERR(ctx)) {
+               pr_err("%s: rockchip clk init failed\n", __func__);
+               iounmap(reg_base);
+               return;
+       }
 
-       rockchip_clk_register_plls(rk3228_pll_clks,
+       rockchip_clk_register_plls(ctx, rk3228_pll_clks,
                                   ARRAY_SIZE(rk3228_pll_clks),
                                   RK3228_GRF_SOC_STATUS0);
-       rockchip_clk_register_branches(rk3228_clk_branches,
+       rockchip_clk_register_branches(ctx, rk3228_clk_branches,
                                  ARRAY_SIZE(rk3228_clk_branches));
        rockchip_clk_protect_critical(rk3228_critical_clocks,
                                      ARRAY_SIZE(rk3228_critical_clocks));
 
-       rockchip_clk_register_armclk(ARMCLK, "armclk",
+       rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
                        mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
                        &rk3228_cpuclk_data, rk3228_cpuclk_rates,
                        ARRAY_SIZE(rk3228_cpuclk_rates));
@@ -651,6 +660,8 @@ static void __init rk3228_clk_init(struct device_node *np)
        rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
                                  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
-       rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
+       rockchip_register_restart_notifier(ctx, RK3228_GLB_SRST_FST, NULL);
+
+       rockchip_clk_of_add_provider(np, ctx);
 }
 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);