Merge branch 'late/dt' into next/dt2

[cascardo/linux.git] / drivers / clk / tegra / clk-tegra20.c

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index f215bf1..8292a00 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -86,8 +86,8 @@
 #define PLLE_BASE 0xe8
 #define PLLE_MISC 0xec
 
-#define PLL_BASE_LOCK 27
-#define PLLE_MISC_LOCK 11
+#define PLL_BASE_LOCK BIT(27)
+#define PLLE_MISC_LOCK BIT(11)
 
 #define PLL_MISC_LOCK_ENABLE 18
 #define PLLDU_MISC_LOCK_ENABLE 22
@@ -380,7 +380,7 @@ static struct tegra_clk_pll_params pll_c_params = {
        .vco_max = 1400000000,
        .base_reg = PLLC_BASE,
        .misc_reg = PLLC_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
 };
@@ -394,7 +394,7 @@ static struct tegra_clk_pll_params pll_m_params = {
        .vco_max = 1200000000,
        .base_reg = PLLM_BASE,
        .misc_reg = PLLM_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
 };
@@ -408,7 +408,7 @@ static struct tegra_clk_pll_params pll_p_params = {
        .vco_max = 1400000000,
        .base_reg = PLLP_BASE,
        .misc_reg = PLLP_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
 };
@@ -422,7 +422,7 @@ static struct tegra_clk_pll_params pll_a_params = {
        .vco_max = 1400000000,
        .base_reg = PLLA_BASE,
        .misc_reg = PLLA_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
 };
@@ -436,7 +436,7 @@ static struct tegra_clk_pll_params pll_d_params = {
        .vco_max = 1000000000,
        .base_reg = PLLD_BASE,
        .misc_reg = PLLD_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
        .lock_delay = 1000,
 };
@@ -456,7 +456,7 @@ static struct tegra_clk_pll_params pll_u_params = {
        .vco_max = 960000000,
        .base_reg = PLLU_BASE,
        .misc_reg = PLLU_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
        .lock_delay = 1000,
        .pdiv_tohw = pllu_p,
@@ -471,7 +471,7 @@ static struct tegra_clk_pll_params pll_x_params = {
        .vco_max = 1200000000,
        .base_reg = PLLX_BASE,
        .misc_reg = PLLX_MISC,
-       .lock_bit_idx = PLL_BASE_LOCK,
+       .lock_mask = PLL_BASE_LOCK,
        .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
        .lock_delay = 300,
 };
@@ -485,7 +485,7 @@ static struct tegra_clk_pll_params pll_e_params = {
        .vco_max = 0,
        .base_reg = PLLE_BASE,
        .misc_reg = PLLE_MISC,
-       .lock_bit_idx = PLLE_MISC_LOCK,
+       .lock_mask = PLLE_MISC_LOCK,
        .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
        .lock_delay = 0,
 };
@@ -710,7 +710,7 @@ static void tegra20_pll_init(void)
        clks[pll_a_out0] = clk;
 
        /* PLLE */
-       clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL,
+       clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
                             0, 100000000, &pll_e_params,
                             0, pll_e_freq_table, NULL);
        clk_register_clkdev(clk, "pll_e", NULL);
@@ -1019,7 +1019,7 @@ static void __init tegra20_periph_clk_init(void)
                data = &tegra_periph_clk_list[i];
                clk = tegra_clk_register_periph(data->name, data->parent_names,
                                data->num_parents, &data->periph,
-                               clk_base, data->offset);
+                               clk_base, data->offset, data->flags);
                clk_register_clkdev(clk, data->con_id, data->dev_id);
                clks[data->clk_id] = clk;
        }