Merge tag 'metag-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan...

[cascardo/linux.git] / drivers / cpufreq / exynos4210-cpufreq.c

diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index 6384e5b..61a5431 100644 (file)
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -16,6 +16,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/cpufreq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include "exynos-cpufreq.h"
 
@@ -23,6 +25,7 @@ static struct clk *cpu_clk;
 static struct clk *moutcore;
 static struct clk *mout_mpll;
 static struct clk *mout_apll;
+static struct exynos_dvfs_info *cpufreq;
 
 static unsigned int exynos4210_volt_table[] = {
        1250000, 1150000, 1050000, 975000, 950000,
@@ -60,20 +63,20 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
 
        tmp = apll_freq_4210[div_index].clk_div_cpu0;
 
-       __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+       __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
 
        do {
-               tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+               tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
        } while (tmp & 0x1111111);
 
        /* Change Divider - CPU1 */
 
        tmp = apll_freq_4210[div_index].clk_div_cpu1;
 
-       __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+       __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
 
        do {
-               tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+               tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
        } while (tmp & 0x11);
 }
 
@@ -85,7 +88,7 @@ static void exynos4210_set_apll(unsigned int index)
        clk_set_parent(moutcore, mout_mpll);
 
        do {
-               tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+               tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
                        >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
                tmp &= 0x7;
        } while (tmp != 0x2);
@@ -96,7 +99,7 @@ static void exynos4210_set_apll(unsigned int index)
        clk_set_parent(moutcore, mout_apll);
 
        do {
-               tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+               tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
                tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
        } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 }
@@ -115,8 +118,30 @@ static void exynos4210_set_frequency(unsigned int old_index,
 
 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 {
+       struct device_node *np;
        unsigned long rate;
 
+       /*
+        * HACK: This is a temporary workaround to get access to clock
+        * controller registers directly and remove static mappings and
+        * dependencies on platform headers. It is necessary to enable
+        * Exynos multi-platform support and will be removed together with
+        * this whole driver as soon as Exynos gets migrated to use
+        * cpufreq-cpu0 driver.
+        */
+       np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
+       if (!np) {
+               pr_err("%s: failed to find clock controller DT node\n",
+                       __func__);
+               return -ENODEV;
+       }
+
+       info->cmu_regs = of_iomap(np, 0);
+       if (!info->cmu_regs) {
+               pr_err("%s: failed to map CMU registers\n", __func__);
+               return -EFAULT;
+       }
+
        cpu_clk = clk_get(NULL, "armclk");
        if (IS_ERR(cpu_clk))
                return PTR_ERR(cpu_clk);
@@ -143,6 +168,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
        info->freq_table = exynos4210_freq_table;
        info->set_freq = exynos4210_set_frequency;
 
+       cpufreq = info;
+
        return 0;
 
 err_mout_apll: