drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)

[cascardo/linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v8_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index f5a42ab..17df5c2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2078,7 +2078,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 
        adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
        adev->gfx.config.mem_max_burst_length_bytes = 256;
-       if (adev->flags & AMDGPU_IS_APU) {
+       if (adev->flags & AMD_IS_APU) {
                /* Get memory bank mapping mode. */
                tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
                dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
@@ -3135,7 +3135,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
                                WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
                                       AMDGPU_DOORBELL_KIQ << 2);
                                WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
-                                               0x7FFFF << 2);
+                                      AMDGPU_DOORBELL_MEC_RING7 << 2);
                        }
                        tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
                        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,