drm/amdgpu: update golden setting of stoney

[cascardo/linux.git] / drivers / gpu / drm / amd / amdgpu / gmc_v8_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9945d5b..2aee2c6 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -41,6 +41,7 @@
 
 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
+static int gmc_v8_0_wait_for_idle(void *handle);
 
 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
@@ -102,6 +103,11 @@ static const u32 stoney_mgcg_cgcg_init[] =
        mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 };
 
+static const u32 golden_settings_stoney_common[] =
+{
+       mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
+       mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
+};
 
 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
@@ -141,50 +147,24 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
                amdgpu_program_register_sequence(adev,
                                                 stoney_mgcg_cgcg_init,
                                                 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+               amdgpu_program_register_sequence(adev,
+                                                golden_settings_stoney_common,
+                                                (const u32)ARRAY_SIZE(golden_settings_stoney_common));
                break;
        default:
                break;
        }
 }
 
-/**
- * gmc8_mc_wait_for_idle - wait for MC idle callback.
- *
- * @adev: amdgpu_device pointer
- *
- * Wait for the MC (memory controller) to be idle.
- * (evergreen+).
- * Returns 0 if the MC is idle, -1 if not.
- */
-int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev)
-{
-       unsigned i;
-       u32 tmp;
-
-       for (i = 0; i < adev->usec_timeout; i++) {
-               /* read MC_STATUS */
-               tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK |
-                                              SRBM_STATUS__MCB_BUSY_MASK |
-                                              SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
-                                              SRBM_STATUS__MCC_BUSY_MASK |
-                                              SRBM_STATUS__MCD_BUSY_MASK |
-                                              SRBM_STATUS__VMC1_BUSY_MASK);
-               if (!tmp)
-                       return 0;
-               udelay(1);
-       }
-       return -1;
-}
-
-void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
-                     struct amdgpu_mode_mc_save *save)
+static void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
+                            struct amdgpu_mode_mc_save *save)
 {
        u32 blackout;
 
        if (adev->mode_info.num_crtc)
                amdgpu_display_stop_mc_access(adev, save);
 
-       amdgpu_asic_wait_for_mc_idle(adev);
+       gmc_v8_0_wait_for_idle(adev);
 
        blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
        if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
@@ -199,8 +179,8 @@ void gmc_v8_0_mc_stop(struct amdgpu_device *adev,
        udelay(100);
 }
 
-void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
-                       struct amdgpu_mode_mc_save *save)
+static void gmc_v8_0_mc_resume(struct amdgpu_device *adev,
+                              struct amdgpu_mode_mc_save *save)
 {
        u32 tmp;
 
@@ -393,7 +373,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
                amdgpu_display_set_vga_render_state(adev, false);
 
        gmc_v8_0_mc_stop(adev, &save);
-       if (amdgpu_asic_wait_for_mc_idle(adev)) {
+       if (gmc_v8_0_wait_for_idle((void *)adev)) {
                dev_warn(adev->dev, "Wait for MC idle timedout !\n");
        }
        /* Update configuration */
@@ -413,7 +393,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
        WREG32(mmMC_VM_AGP_BASE, 0);
        WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
        WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
-       if (amdgpu_asic_wait_for_mc_idle(adev)) {
+       if (gmc_v8_0_wait_for_idle((void *)adev)) {
                dev_warn(adev->dev, "Wait for MC idle timedout !\n");
        }
        gmc_v8_0_mc_resume(adev, &save);
@@ -1140,7 +1120,7 @@ static int gmc_v8_0_soft_reset(void *handle)
 
        if (srbm_soft_reset) {
                gmc_v8_0_mc_stop(adev, &save);
-               if (gmc_v8_0_wait_for_idle(adev)) {
+               if (gmc_v8_0_wait_for_idle((void *)adev)) {
                        dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
                }