struct _ATOM_PPLIB_SI_CLOCK_INFO si;
};
-const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
+static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
{
R600_UTC_DFLT_00,
R600_UTC_DFLT_01,
R600_UTC_DFLT_14,
};
-const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
+static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
{
R600_DTC_DFLT_00,
R600_DTC_DFLT_01,
true
};
-struct si_cac_config_reg cac_weights_pitcairn[] =
+static const struct si_cac_config_reg cac_weights_pitcairn[] =
{
{ 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
{ 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
true
};
-struct si_cac_config_reg cac_weights_oland[] =
+static const struct si_cac_config_reg cac_weights_oland[] =
{
{ 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
{ 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
true
};
-struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
-struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
-struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
-struct si_ps *si_get_ps(struct amdgpu_ps *rps);
+static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
+static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
+static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
+static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
static int si_populate_voltage_value(struct amdgpu_device *adev,
const struct atom_voltage_table *table,
static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
-extern u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg);
-
static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
{
struct si_power_info *pi = adev->pm.dpm.priv;
}
}
-struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
+static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
{
struct rv7xx_power_info *pi = adev->pm.dpm.priv;
return pi;
}
-struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
+static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
{
struct ni_power_info *pi = adev->pm.dpm.priv;
return pi;
}
-struct si_ps *si_get_ps(struct amdgpu_ps *aps)
+static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
{
struct si_ps *ps = aps->ps_priv;
smc_table->dpm2Params.SafePowerLimit =
cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
- ret = si_copy_bytes_to_smc(adev,
- (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
- offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
- (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
- sizeof(u32) * 3,
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev,
+ (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
+ offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
+ (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
+ sizeof(u32) * 3,
+ si_pi->sram_end);
if (ret)
return ret;
papm_parm->PlatformPowerLimit = 0xffffffff;
papm_parm->NearTDPLimitPAPM = 0xffffffff;
- ret = si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
- (u8 *)papm_parm,
- sizeof(PP_SIslands_PAPMParameters),
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
+ (u8 *)papm_parm,
+ sizeof(PP_SIslands_PAPMParameters),
+ si_pi->sram_end);
if (ret)
return ret;
}
smc_table->dpm2Params.SafePowerLimit =
cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
- ret = si_copy_bytes_to_smc(adev,
- (si_pi->state_table_start +
- offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
- offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
- (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
- sizeof(u32) * 2,
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev,
+ (si_pi->state_table_start +
+ offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
+ offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
+ (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
+ sizeof(u32) * 2,
+ si_pi->sram_end);
if (ret)
return ret;
}
if (ni_pi->enable_power_containment) {
if (enable) {
if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
- smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
if (smc_result != PPSMC_Result_OK) {
ret = -EINVAL;
ni_pi->pc_enabled = false;
}
}
} else {
- smc_result = si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
if (smc_result != PPSMC_Result_OK)
ret = -EINVAL;
ni_pi->pc_enabled = false;
dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
}
- ret = si_copy_bytes_to_smc(adev, si_pi->dte_table_start, (u8 *)dte_tables,
- sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
+ (u8 *)dte_tables,
+ sizeof(Smc_SIslands_DTE_Configuration),
+ si_pi->sram_end);
kfree(dte_tables);
return ret;
cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
- ret = si_copy_bytes_to_smc(adev, si_pi->cac_table_start, (u8 *)cac_tables,
- sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
+ (u8 *)cac_tables,
+ sizeof(PP_SIslands_CacConfig),
+ si_pi->sram_end);
if (ret)
goto done_free;
kfree(cac_tables);
- return 0;
+ return ret;
}
static int si_program_cac_config_registers(struct amdgpu_device *adev,
if (enable) {
if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
if (ni_pi->support_cac_long_term_average) {
- smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
if (smc_result != PPSMC_Result_OK)
ni_pi->support_cac_long_term_average = false;
}
- smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
if (smc_result != PPSMC_Result_OK) {
ret = -EINVAL;
ni_pi->cac_enabled = false;
}
if (si_pi->enable_dte) {
- smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
if (smc_result != PPSMC_Result_OK)
ret = -EINVAL;
}
}
} else if (ni_pi->cac_enabled) {
if (si_pi->enable_dte)
- smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
- smc_result = si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
ni_pi->cac_enabled = false;
if (ni_pi->support_cac_long_term_average)
- smc_result = si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
+ smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
}
}
return ret;
if (!ret)
- ret = si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
- (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
+ (u8 *)spll_table,
+ sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
+ si_pi->sram_end);
if (ret)
ni_pi->enable_power_containment = false;
/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
{ PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
+ { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
+ { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
+ { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
{ 0, 0, 0, 0 },
};
max_sclk, requested_sclk);
}
-void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
- u32 *max_clock)
+static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
+ u32 *max_clock)
{
u32 i, clock = 0;
}
++p;
}
+ /* limit mclk on all R7 370 parts for stability */
+ if (adev->pdev->device == 0x6811 &&
+ adev->pdev->revision == 0x81)
+ max_mclk = 120000;
+ /* limit sclk/mclk on Jet parts for stability */
+ if (adev->pdev->device == 0x6665 &&
+ adev->pdev->revision == 0xc3) {
+ max_sclk = 75000;
+ max_mclk = 80000;
+ }
+ /* Limit clocks for some HD8600 parts */
+ if (adev->pdev->device == 0x6660 &&
+ adev->pdev->revision == 0x83) {
+ max_sclk = 75000;
+ max_mclk = 80000;
+ }
if (rps->vce_active) {
rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
{
struct si_power_info *si_pi = si_get_pi(adev);
- return si_read_smc_sram_dword(adev,
- si_pi->soft_regs_start + reg_offset, value,
- si_pi->sram_end);
+ return amdgpu_si_read_smc_sram_dword(adev,
+ si_pi->soft_regs_start + reg_offset, value,
+ si_pi->sram_end);
}
#endif
{
struct si_power_info *si_pi = si_get_pi(adev);
- return si_write_smc_sram_dword(adev,
- si_pi->soft_regs_start + reg_offset,
- value, si_pi->sram_end);
+ return amdgpu_si_write_smc_sram_dword(adev,
+ si_pi->soft_regs_start + reg_offset,
+ value, si_pi->sram_end);
}
static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
PPSMC_Result ret;
if (thermal_level == 0) {
- ret = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
+ ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
if (ret == PPSMC_Result_OK)
return 0;
else
static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
{
if (ac_power)
- return (si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
0 : -EINVAL;
return 0;
PPSMC_Msg msg, u32 parameter)
{
WREG32(SMC_SCRATCH0, parameter);
- return si_send_msg_to_smc(adev, msg);
+ return amdgpu_si_send_msg_to_smc(adev, msg);
}
static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
{
- if (si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
+ if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
return -EINVAL;
return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
#if 0
static int si_set_boot_state(struct amdgpu_device *adev)
{
- return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
#endif
static int si_set_sw_state(struct amdgpu_device *adev)
{
- return (si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
static int si_halt_smc(struct amdgpu_device *adev)
{
- if (si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
+ if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
return -EINVAL;
- return (si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
+ return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
static int si_resume_smc(struct amdgpu_device *adev)
{
- if (si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
+ if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
return -EINVAL;
- return (si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
static void si_dpm_start_smc(struct amdgpu_device *adev)
{
- si_program_jump_on_start(adev);
- si_start_smc(adev);
- si_smc_clock(adev, true);
+ amdgpu_si_program_jump_on_start(adev);
+ amdgpu_si_start_smc(adev);
+ amdgpu_si_smc_clock(adev, true);
}
static void si_dpm_stop_smc(struct amdgpu_device *adev)
{
- si_reset_smc(adev);
- si_smc_clock(adev, false);
+ amdgpu_si_reset_smc(adev);
+ amdgpu_si_smc_clock(adev, false);
}
static int si_process_firmware_header(struct amdgpu_device *adev)
u32 tmp;
int ret;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->state_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->soft_regs_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->mc_reg_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->fan_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->arb_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->cac_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->dte_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
si_pi->spll_table_start = tmp;
- ret = si_read_smc_sram_dword(adev,
- SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
- SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev,
+ SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
+ SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
PPSMC_Msg msg = has_display ?
PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
- return (si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
WREG32(CG_FTV, 0);
}
-u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
+static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
{
u8 mc_para_index;
return mc_para_index;
}
-u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
+static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
{
u8 mc_para_index;
{
struct si_power_info *si_pi = si_get_pi(adev);
- si_reset_smc(adev);
- si_smc_clock(adev, false);
+ amdgpu_si_reset_smc(adev);
+ amdgpu_si_smc_clock(adev, false);
- return si_load_smc_ucode(adev, si_pi->sram_end);
+ return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
}
static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
&adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
- table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
+ table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
u32 tmp;
int ret;
- ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
tmp &= 0x00FFFFFF;
tmp |= MC_CG_ARB_FREQ_F1 << 24;
- return si_write_smc_sram_dword(adev, si_pi->arb_table_start, tmp, si_pi->sram_end);
+ return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
+ tmp, si_pi->sram_end);
}
static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
static int si_reset_to_default(struct amdgpu_device *adev)
{
- return (si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
u32 tmp;
int ret;
- ret = si_read_smc_sram_dword(adev, si_pi->arb_table_start,
- &tmp, si_pi->sram_end);
+ ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
+ &tmp, si_pi->sram_end);
if (ret)
return ret;
ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
if (ret)
break;
- ret = si_copy_bytes_to_smc(adev,
- si_pi->arb_table_start +
- offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
- sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
- (u8 *)&arb_regs,
- sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev,
+ si_pi->arb_table_start +
+ offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
+ sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
+ (u8 *)&arb_regs,
+ sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
+ si_pi->sram_end);
if (ret)
break;
}
si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
ulv->volt_change_delay);
- ret = si_copy_bytes_to_smc(adev,
- si_pi->arb_table_start +
- offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
- sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
- (u8 *)&arb_regs,
- sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev,
+ si_pi->arb_table_start +
+ offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
+ sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
+ (u8 *)&arb_regs,
+ sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
+ si_pi->sram_end);
return ret;
}
table->ULVState = table->initialState;
}
- return si_copy_bytes_to_smc(adev, si_pi->state_table_start,
- (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
- si_pi->sram_end);
+ return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
+ (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
+ si_pi->sram_end);
}
static int si_calculate_sclk_params(struct amdgpu_device *adev,
struct si_ulv_param *ulv = &si_pi->ulv;
if (ulv->supported)
- return (si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
0 : -EINVAL;
return 0;
if (ulv->supported) {
if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
- return (si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
0 : -EINVAL;
}
return 0;
if (ret)
return ret;
- return si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
- state_size, si_pi->sram_end);
+ return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
+ state_size, si_pi->sram_end);
}
static int si_upload_ulv_state(struct amdgpu_device *adev)
ret = si_populate_ulv_state(adev, smc_state);
if (!ret)
- ret = si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
- state_size, si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
+ state_size, si_pi->sram_end);
}
return ret;
si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
- return si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
- (u8 *)smc_mc_reg_table,
- sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
+ return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
+ (u8 *)smc_mc_reg_table,
+ sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
}
static int si_upload_mc_reg_table(struct amdgpu_device *adev,
si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
- return si_copy_bytes_to_smc(adev, address,
- (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
- sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
- si_pi->sram_end);
+ return amdgpu_si_copy_bytes_to_smc(adev, address,
+ (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
+ sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
+ si_pi->sram_end);
}
static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
if (eg_pi->sclk_deep_sleep) {
if (ds_status_on)
- return (si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
PPSMC_Result_OK) ?
0 : -EINVAL;
else
- return (si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
+ return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
PPSMC_Result_OK) ? 0 : -EINVAL;
}
return 0;
ret = si_patch_single_dependency_table_based_on_leakage(adev,
&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
+ if (ret)
+ DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
ret = si_patch_single_dependency_table_based_on_leakage(adev,
&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
+ if (ret)
+ DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
ret = si_patch_single_dependency_table_based_on_leakage(adev,
&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
+ if (ret)
+ DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
return ret;
}
thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
WREG32(CG_THERMAL_INT, thermal_int);
- result = si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
+ result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
if (result != PPSMC_Result_OK) {
DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
return -EINVAL;
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
fan_table.temp_src = (uint8_t)tmp;
- ret = si_copy_bytes_to_smc(adev,
- si_pi->fan_table_start,
- (u8 *)(&fan_table),
- sizeof(fan_table),
- si_pi->sram_end);
+ ret = amdgpu_si_copy_bytes_to_smc(adev,
+ si_pi->fan_table_start,
+ (u8 *)(&fan_table),
+ sizeof(fan_table),
+ si_pi->sram_end);
if (ret) {
DRM_ERROR("Failed to load fan table to the SMC.");
adev->pm.dpm.fan.ucode_fan_control = false;
}
- return 0;
+ return ret;
}
static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
struct si_power_info *si_pi = si_get_pi(adev);
PPSMC_Result ret;
- ret = si_send_msg_to_smc(adev, PPSMC_StartFanControl);
+ ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
if (ret == PPSMC_Result_OK) {
si_pi->fan_is_controlled_by_smc = true;
return 0;
struct si_power_info *si_pi = si_get_pi(adev);
PPSMC_Result ret;
- ret = si_send_msg_to_smc(adev, PPSMC_StopFanControl);
+ ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
if (ret == PPSMC_Result_OK) {
si_pi->fan_is_controlled_by_smc = false;
struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
int ret;
- if (si_is_smc_running(adev))
+ if (amdgpu_si_is_smc_running(adev))
return -EINVAL;
if (pi->voltage_control || si_pi->voltage_control_svi2)
si_enable_voltage_control(adev, true);
struct rv7xx_power_info *pi = rv770_get_pi(adev);
struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
- if (!si_is_smc_running(adev))
+ if (!amdgpu_si_is_smc_running(adev))
return;
si_thermal_stop_thermal_controller(adev);
si_disable_ulv(adev);
}
static int si_dpm_process_interrupt(struct amdgpu_device *adev,
- struct amdgpu_irq_src *source,
+ struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
bool queue_thermal = false;
projects / cascardo / linux.git / blobdiff