drm/amd/powerplay: Use defined constants for minium engine clock

[cascardo/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_hwmgr.c

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 55a006d..c574afd 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -465,14 +465,14 @@ static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
                        table_info->vdd_dep_on_mclk;
 
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
-               "VDD dependency on SCLK table is missing.       \
+               "VDD dependency on SCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
-               "VDD dependency on SCLK table has to have is missing.   \
+               "VDD dependency on SCLK table has to have is missing.   \
                This table is mandatory", return -EINVAL);
 
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
-               "VDD dependency on MCLK table is missing.       \
+               "VDD dependency on MCLK table is missing.       \
                This table is mandatory", return -EINVAL);
        PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
                "VDD dependency on MCLK table has to have is missing.    \
@@ -579,6 +579,18 @@ static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
        return 0;
 }
 
+static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+{
+       struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
+
+       if (data->soft_pp_table) {
+               kfree(data->soft_pp_table);
+               data->soft_pp_table = NULL;
+       }
+
+       return phm_hwmgr_backend_fini(hwmgr);
+}
+
 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 {
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@@ -734,7 +746,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
                        data->pcie_lane_cap = (uint32_t)sys_info.value;
        } else {
                /* Ignore return value in here, we are cleaning up a mess. */
-               tonga_hwmgr_backend_fini(hwmgr);
+               fiji_hwmgr_backend_fini(hwmgr);
        }
 
        return 0;
@@ -1891,7 +1903,8 @@ static uint8_t fiji_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
 {
        uint8_t i;
        uint32_t temp;
-       uint32_t min = clock_insr > 2500 ? clock_insr : 2500;
+       uint32_t min = clock_insr > FIJI_MINIMUM_ENGINE_CLOCK ?
+                       clock_insr : FIJI_MINIMUM_ENGINE_CLOCK;
 
        PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
        for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
@@ -3377,7 +3390,7 @@ static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
                                DPM_EVENT_SRC, src);
                PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
                                THERMAL_PROTECTION_DIS,
-                               phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+                               !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
                                                PHM_PlatformCaps_ThermalController));
        } else
                PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
@@ -5096,24 +5109,40 @@ static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
 {
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
-       *table = (char *)&data->smc_state_table;
+       if (!data->soft_pp_table) {
+               data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+               if (!data->soft_pp_table)
+                       return -ENOMEM;
+               memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
+                               hwmgr->soft_pp_table_size);
+       }
+
+       *table = (char *)&data->soft_pp_table;
 
-       return sizeof(struct SMU73_Discrete_DpmTable);
+       return hwmgr->soft_pp_table_size;
 }
 
 static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
 {
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
-       void *table = (void *)&data->smc_state_table;
+       if (!data->soft_pp_table) {
+               data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+               if (!data->soft_pp_table)
+                       return -ENOMEM;
+       }
+
+       memcpy(data->soft_pp_table, buf, size);
 
-       memcpy(table, buf, size);
+       hwmgr->soft_pp_table = data->soft_pp_table;
+
+       /* TODO: re-init powerplay to implement modified pptable */
 
        return 0;
 }
 
 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
-               enum pp_clock_type type, int level)
+               enum pp_clock_type type, uint32_t mask)
 {
        struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
@@ -5125,20 +5154,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
                if (!data->sclk_dpm_key_disabled)
                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
                                        PPSMC_MSG_SCLKDPM_SetEnabledMask,
-                                       (1 << level));
+                                       data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
                break;
+
        case PP_MCLK:
                if (!data->mclk_dpm_key_disabled)
                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
                                        PPSMC_MSG_MCLKDPM_SetEnabledMask,
-                                       (1 << level));
+                                       data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
                break;
+
        case PP_PCIE:
+       {
+               uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
+               uint32_t level = 0;
+
+               while (tmp >>= 1)
+                       level++;
+
                if (!data->pcie_dpm_key_disabled)
                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
                                        PPSMC_MSG_PCIeDPM_ForceLevel,
-                                       (1 << level));
+                                       level);
                break;
+       }
        default:
                break;
        }
@@ -5274,7 +5313,7 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
 
 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
        .backend_init = &fiji_hwmgr_backend_init,
-       .backend_fini = &tonga_hwmgr_backend_fini,
+       .backend_fini = &fiji_hwmgr_backend_fini,
        .asic_setup = &fiji_setup_asic_task,
        .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
        .force_dpm_level = &fiji_dpm_force_dpm_level,