drm/i915: Reduce CHV DDL multiplier to 16/8

[cascardo/linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f67e290..1e5ce1b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -139,6 +139,19 @@
 #define GEN8_RING_PDP_UDW(ring, n)     ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
 #define GEN8_RING_PDP_LDW(ring, n)     ((ring)->mmio_base+0x270 + (n) * 8)
 
+#define GEN8_R_PWR_CLK_STATE           0x20C8
+#define   GEN8_RPCS_ENABLE             (1 << 31)
+#define   GEN8_RPCS_S_CNT_ENABLE       (1 << 18)
+#define   GEN8_RPCS_S_CNT_SHIFT                15
+#define   GEN8_RPCS_S_CNT_MASK         (0x7 << GEN8_RPCS_S_CNT_SHIFT)
+#define   GEN8_RPCS_SS_CNT_ENABLE      (1 << 11)
+#define   GEN8_RPCS_SS_CNT_SHIFT       8
+#define   GEN8_RPCS_SS_CNT_MASK                (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
+#define   GEN8_RPCS_EU_MAX_SHIFT       4
+#define   GEN8_RPCS_EU_MAX_MASK                (0xf << GEN8_RPCS_EU_MAX_SHIFT)
+#define   GEN8_RPCS_EU_MIN_SHIFT       0
+#define   GEN8_RPCS_EU_MIN_MASK                (0xf << GEN8_RPCS_EU_MIN_SHIFT)
+
 #define GAM_ECOCHK                     0x4090
 #define   BDW_DISABLE_HDC_INVALIDATION (1<<25)
 #define   ECOCHK_SNB_BIT               (1<<10)
@@ -1338,6 +1351,8 @@ enum skl_disp_power_wells {
 #define   GEN6_WIZ_HASHING_16x4                                GEN6_WIZ_HASHING(1, 0)
 #define   GEN6_WIZ_HASHING_MASK                                GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE            (1 << 5)
+#define   GEN9_IZ_HASHING_MASK(slice)                  (0x3 << (slice * 2))
+#define   GEN9_IZ_HASHING(slice, val)                  ((val) << (slice * 2))
 
 #define GFX_MODE       0x02520
 #define GFX_MODE_GEN7  0x0229c
@@ -1516,6 +1531,17 @@ enum skl_disp_power_wells {
 #define   CHV_FGT_EU_DIS_SS1_R1_SHIFT  28
 #define   CHV_FGT_EU_DIS_SS1_R1_MASK   (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
 
+#define GEN8_FUSE2                     0x9120
+#define   GEN8_F2_S_ENA_SHIFT          25
+#define   GEN8_F2_S_ENA_MASK           (0x7 << GEN8_F2_S_ENA_SHIFT)
+
+#define   GEN9_F2_SS_DIS_SHIFT         20
+#define   GEN9_F2_SS_DIS_MASK          (0xf << GEN9_F2_SS_DIS_SHIFT)
+
+#define GEN8_EU_DISABLE0               0x9134
+#define GEN8_EU_DISABLE1               0x9138
+#define GEN8_EU_DISABLE2               0x913c
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL    0x12050
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
@@ -2993,7 +3019,7 @@ enum skl_disp_power_wells {
 
 /* Video Data Island Packet control */
 #define VIDEO_DIP_DATA         0x61178
-/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
+/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE  32
@@ -3890,6 +3916,7 @@ enum skl_disp_power_wells {
 #define   PIPECONF_INTERLACE_MODE_MASK         (7 << 21)
 #define   PIPECONF_EDP_RR_MODE_SWITCH          (1 << 20)
 #define   PIPECONF_CXSR_DOWNCLOCK      (1<<16)
+#define   PIPECONF_EDP_RR_MODE_SWITCH_VLV      (1 << 14)
 #define   PIPECONF_COLOR_RANGE_SELECT  (1 << 13)
 #define   PIPECONF_BPC_MASK    (0x7 << 5)
 #define   PIPECONF_8BPC                (0<<5)
@@ -4178,6 +4205,7 @@ enum skl_disp_power_wells {
 #define   DSPFW_PLANEA_WM1_HI_MASK     (1<<0)
 
 /* drain latency register values*/
+#define DRAIN_LATENCY_PRECISION_8      8
 #define DRAIN_LATENCY_PRECISION_16     16
 #define DRAIN_LATENCY_PRECISION_32     32
 #define DRAIN_LATENCY_PRECISION_64     64
@@ -6198,6 +6226,26 @@ enum skl_disp_power_wells {
 #define   GEN6_RC6                     3
 #define   GEN6_RC7                     4
 
+#define GEN9_SLICE0_PGCTL_ACK          0x804c
+#define GEN9_SLICE1_PGCTL_ACK          0x8050
+#define GEN9_SLICE2_PGCTL_ACK          0x8054
+#define   GEN9_PGCTL_SLICE_ACK         (1 << 0)
+
+#define GEN9_SLICE0_SS01_EU_PGCTL_ACK  0x805c
+#define GEN9_SLICE0_SS23_EU_PGCTL_ACK  0x8060
+#define GEN9_SLICE1_SS01_EU_PGCTL_ACK  0x8064
+#define GEN9_SLICE1_SS23_EU_PGCTL_ACK  0x8068
+#define GEN9_SLICE2_SS01_EU_PGCTL_ACK  0x806c
+#define GEN9_SLICE2_SS23_EU_PGCTL_ACK  0x8070
+#define   GEN9_PGCTL_SSA_EU08_ACK      (1 << 0)
+#define   GEN9_PGCTL_SSA_EU19_ACK      (1 << 2)
+#define   GEN9_PGCTL_SSA_EU210_ACK     (1 << 4)
+#define   GEN9_PGCTL_SSA_EU311_ACK     (1 << 6)
+#define   GEN9_PGCTL_SSB_EU08_ACK      (1 << 8)
+#define   GEN9_PGCTL_SSB_EU19_ACK      (1 << 10)
+#define   GEN9_PGCTL_SSB_EU210_ACK     (1 << 12)
+#define   GEN9_PGCTL_SSB_EU311_ACK     (1 << 14)
+
 #define GEN7_MISCCPCTL                 (0x9424)
 #define   GEN7_DOP_CLOCK_GATE_ENABLE   (1<<0)