drm/nv50-/disp: audit and version PIOR_PWR method

[cascardo/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / nva3.c

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 019124d..38a79a0 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -35,27 +35,17 @@
 
 static struct nouveau_oclass
 nva3_disp_sclass[] = {
-       { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs },
-       { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs },
-       { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs },
-       { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs },
-       { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs },
+       { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
+       { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
+       { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
+       { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
+       { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
        {}
 };
 
 static struct nouveau_omthds
 nva3_disp_base_omthds[] = {
        { HEAD_MTHD(NV50_DISP_SCANOUTPOS)     , nv50_disp_base_scanoutpos },
-       { SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },
-       { SOR_MTHD(NVA3_DISP_SOR_HDA_ELD)     , nv50_sor_mthd },
-       { SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },
-       { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
-       { SOR_MTHD(NV94_DISP_SOR_DP_PWR)      , nv50_sor_mthd },
-       { DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },
-       { DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },
-       { PIOR_MTHD(NV50_DISP_PIOR_PWR)       , nv50_pior_mthd },
-       { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR)  , nv50_pior_mthd },
-       { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR)    , nv50_pior_mthd },
        {},
 };
 
@@ -110,6 +100,7 @@ nva3_disp_oclass = &(struct nv50_disp_impl) {
                .init = _nouveau_disp_init,
                .fini = _nouveau_disp_fini,
        },
+       .base.vblank = &nv50_disp_vblank_func,
        .base.outp =  nv94_disp_outp_sclass,
        .mthd.core = &nv94_disp_mast_mthd_chan,
        .mthd.base = &nv84_disp_sync_mthd_chan,