#include "nv20.h"
#include "regs.h"
+#include <core/gpuobj.h>
#include <engine/fifo.h>
#include <engine/fifo/chan.h>
static const struct nvkm_gr_func
nv34_gr = {
+ .dtor = nv20_gr_dtor,
+ .oneinit = nv20_gr_oneinit,
+ .init = nv30_gr_init,
+ .intr = nv20_gr_intr,
+ .tile = nv20_gr_tile,
.chan_new = nv34_gr_chan_new,
.sclass = {
{ -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */
}
};
-static int
-nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
- struct nvkm_oclass *oclass, void *data, u32 size,
- struct nvkm_object **pobject)
+int
+nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
{
- struct nvkm_device *device = (void *)parent;
- struct nv20_gr *gr;
- int ret;
-
- ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
- *pobject = nv_object(gr);
- if (ret)
- return ret;
-
- gr->base.func = &nv34_gr;
-
- ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true,
- &gr->ctxtab);
- if (ret)
- return ret;
-
- nv_subdev(gr)->unit = 0x00001000;
- nv_subdev(gr)->intr = nv20_gr_intr;
- nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
- return 0;
+ return nv20_gr_new_(&nv34_gr, device, index, pgr);
}
-
-struct nvkm_oclass
-nv34_gr_oclass = {
- .handle = NV_ENGINE(GR, 0x34),
- .ofuncs = &(struct nvkm_ofuncs) {
- .ctor = nv34_gr_ctor,
- .dtor = nv20_gr_dtor,
- .init = nv30_gr_init,
- .fini = _nvkm_gr_fini,
- },
-};