drm/amdgpu/gfx8: enable cp inst/reg error interrupts
[cascardo/linux.git] / drivers / iommu / arm-smmu.c
index 47dc7a7..59ee4b8 100644 (file)
@@ -582,7 +582,7 @@ static void arm_smmu_tlb_inv_context(void *cookie)
 }
 
 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
-                                         bool leaf, void *cookie)
+                                         size_t granule, bool leaf, void *cookie)
 {
        struct arm_smmu_domain *smmu_domain = cookie;
        struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
@@ -597,12 +597,18 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
                if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) {
                        iova &= ~12UL;
                        iova |= ARM_SMMU_CB_ASID(cfg);
-                       writel_relaxed(iova, reg);
+                       do {
+                               writel_relaxed(iova, reg);
+                               iova += granule;
+                       } while (size -= granule);
 #ifdef CONFIG_64BIT
                } else {
                        iova >>= 12;
                        iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48;
-                       writeq_relaxed(iova, reg);
+                       do {
+                               writeq_relaxed(iova, reg);
+                               iova += granule >> 12;
+                       } while (size -= granule);
 #endif
                }
 #ifdef CONFIG_64BIT
@@ -610,7 +616,11 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
                reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
                reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
                              ARM_SMMU_CB_S2_TLBIIPAS2;
-               writeq_relaxed(iova >> 12, reg);
+               iova >>= 12;
+               do {
+                       writeq_relaxed(iova, reg);
+                       iova += granule >> 12;
+               } while (size -= granule);
 #endif
        } else {
                reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
@@ -945,9 +955,7 @@ static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
                free_irq(irq, domain);
        }
 
-       if (smmu_domain->pgtbl_ops)
-               free_io_pgtable_ops(smmu_domain->pgtbl_ops);
-
+       free_io_pgtable_ops(smmu_domain->pgtbl_ops);
        __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
 }
 
@@ -1357,6 +1365,7 @@ static int arm_smmu_add_device(struct device *dev)
        if (IS_ERR(group))
                return PTR_ERR(group);
 
+       iommu_group_put(group);
        return 0;
 }