denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
}
-/* configures the initial ECC settings for the controller */
-static void set_ecc_config(struct denali_nand_info *denali)
-{
-#if SUPPORT_8BITECC
- if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
- (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
- denali_write32(8, denali->flash_reg + ECC_CORRECTION);
-#endif
-
-}
-
/* queries the NAND device to see what ONFI modes it supports. */
static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
{
int i;
-
- denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
-
- while (!((ioread32(denali->flash_reg + INTR_STATUS0) &
- INTR_STATUS0__RST_COMP) |
- (ioread32(denali->flash_reg + INTR_STATUS0) &
- INTR_STATUS0__TIME_OUT)))
- ;
-
- if (ioread32(denali->flash_reg + INTR_STATUS0) &
- INTR_STATUS0__RST_COMP) {
- denali_write32(DEVICE_RESET__BANK1,
- denali->flash_reg + DEVICE_RESET);
- while (!((ioread32(denali->flash_reg + INTR_STATUS1) &
- INTR_STATUS1__RST_COMP) |
- (ioread32(denali->flash_reg + INTR_STATUS1) &
- INTR_STATUS1__TIME_OUT)))
- ;
-
- if (ioread32(denali->flash_reg + INTR_STATUS1) &
- INTR_STATUS1__RST_COMP) {
- denali_write32(DEVICE_RESET__BANK2,
- denali->flash_reg + DEVICE_RESET);
- while (!((ioread32(denali->flash_reg + INTR_STATUS2) &
- INTR_STATUS2__RST_COMP) |
- (ioread32(denali->flash_reg + INTR_STATUS2) &
- INTR_STATUS2__TIME_OUT)))
- ;
-
- if (ioread32(denali->flash_reg + INTR_STATUS2) &
- INTR_STATUS2__RST_COMP) {
- denali_write32(DEVICE_RESET__BANK3,
- denali->flash_reg + DEVICE_RESET);
- while (!((ioread32(denali->flash_reg +
- INTR_STATUS3) &
- INTR_STATUS3__RST_COMP) |
- (ioread32(denali->flash_reg +
- INTR_STATUS3) &
- INTR_STATUS3__TIME_OUT)))
- ;
- } else {
- printk(KERN_ERR "Getting a time out for bank 2!\n");
- }
- } else {
- printk(KERN_ERR "Getting a time out for bank 1!\n");
- }
- }
-
- denali_write32(INTR_STATUS0__TIME_OUT,
- denali->flash_reg + INTR_STATUS0);
- denali_write32(INTR_STATUS1__TIME_OUT,
- denali->flash_reg + INTR_STATUS1);
- denali_write32(INTR_STATUS2__TIME_OUT,
- denali->flash_reg + INTR_STATUS2);
- denali_write32(INTR_STATUS3__TIME_OUT,
- denali->flash_reg + INTR_STATUS3);
-
+ /* we needn't to do a reset here because driver has already
+ * reset all the banks before
+ * */
if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
ONFI_TIMING_MODE__VALUE))
return FAIL;
return PASS;
}
-static void get_samsung_nand_para(struct denali_nand_info *denali)
+static void get_samsung_nand_para(struct denali_nand_info *denali,
+ uint8_t device_id)
{
- uint32_t id_bytes[5];
- int i;
-
- index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90);
- index_addr(denali, (uint32_t)(MODE_11 | 1), 0);
- for (i = 0; i < 5; i++)
- index_addr_read_data(denali, (uint32_t)(MODE_11 | 2),
- &id_bytes[i]);
-
- nand_dbg_print(NAND_DBG_DEBUG,
- "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
- id_bytes[0], id_bytes[1], id_bytes[2],
- id_bytes[3], id_bytes[4]);
-
- if ((id_bytes[1] & 0xff) == 0xd3) { /* Samsung K9WAG08U1A */
+ if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
/* Set timing register values according to datasheet */
denali_write32(5, denali->flash_reg + ACC_CLKS);
denali_write32(20, denali->flash_reg + RE_2_WE);
if (FAIL == get_onfi_nand_para(denali))
return FAIL;
} else if (maf_id == 0xEC) { /* Samsung NAND */
- get_samsung_nand_para(denali);
+ get_samsung_nand_para(denali, device_id);
} else if (maf_id == 0x98) { /* Toshiba NAND */
get_toshiba_nand_para(denali);
} else if (maf_id == 0xAD) { /* Hynix NAND */
ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
ioread32(denali->flash_reg + CS_SETUP_CNT));
- set_ecc_config(denali);
-
find_valid_banks(denali);
detect_partition_feature(denali);
/* Initialization code to bring the device up to a known good state */
static void denali_hw_init(struct denali_nand_info *denali)
{
+ /* tell driver how many bit controller will skip before
+ * writing ECC code in OOB, this register may be already
+ * set by firmware. So we read this value out.
+ * if this value is 0, just let it be.
+ * */
+ denali->bbtskipbytes = ioread32(denali->flash_reg +
+ SPARE_AREA_SKIP_BYTES);
denali_irq_init(denali);
denali_nand_reset(denali);
denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
denali_write32(1, denali->flash_reg + ECC_ENABLE);
}
-/* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */
-#define ECC_BYTES_SLC (4 * (2048 / ECC_SECTOR_SIZE))
-static struct nand_ecclayout nand_oob_slc = {
- .eccbytes = 4,
- .eccpos = { 0, 1, 2, 3 }, /* not used */
- .oobfree = {
- {
- .offset = ECC_BYTES_SLC,
- .length = 64 - ECC_BYTES_SLC
- }
- }
+/* Althogh controller spec said SLC ECC is forceb to be 4bit,
+ * but denali controller in MRST only support 15bit and 8bit ECC
+ * correction
+ * */
+#define ECC_8BITS 14
+static struct nand_ecclayout nand_8bit_oob = {
+ .eccbytes = 14,
};
-#define ECC_BYTES_MLC (14 * (2048 / ECC_SECTOR_SIZE))
-static struct nand_ecclayout nand_oob_mlc_14bit = {
- .eccbytes = 14,
- .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
- .oobfree = {
- {
- .offset = ECC_BYTES_MLC,
- .length = 64 - ECC_BYTES_MLC
- }
- }
+#define ECC_15BITS 26
+static struct nand_ecclayout nand_15bit_oob = {
+ .eccbytes = 26,
};
static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
.pattern = mirror_pattern,
};
-/* initalize driver data structures */
+/* initialize driver data structures */
void denali_drv_init(struct denali_nand_info *denali)
{
denali->idx = 0;
ret = pci_enable_device(dev);
if (ret) {
printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
- goto failed_enable;
+ goto failed_alloc_memery;
}
if (id->driver_data == INTEL_CE4100) {
printk(KERN_ERR "Intel CE4100 only supports"
" ONFI timing mode 1 or below\n");
ret = -EINVAL;
- goto failed_enable;
+ goto failed_enable_dev;
}
denali->platform = INTEL_CE4100;
mem_base = pci_resource_start(dev, 0);
} else {
denali->platform = INTEL_MRST;
csr_base = pci_resource_start(dev, 0);
- csr_len = pci_resource_start(dev, 0);
+ csr_len = pci_resource_len(dev, 0);
mem_base = pci_resource_start(dev, 1);
mem_len = pci_resource_len(dev, 1);
if (!mem_len) {
if (ret) {
printk(KERN_ERR "Spectra: no usable DMA configuration\n");
- goto failed_enable;
+ goto failed_enable_dev;
}
denali->buf.dma_buf =
pci_map_single(dev, denali->buf.buf,
if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
- goto failed_enable;
+ goto failed_enable_dev;
}
pci_set_master(dev);
ret = pci_request_regions(dev, DENALI_NAND_NAME);
if (ret) {
printk(KERN_ERR "Spectra: Unable to request memory regions\n");
- goto failed_req_csr;
+ goto failed_dma_map;
}
denali->flash_reg = ioremap_nocache(csr_base, csr_len);
if (!denali->flash_reg) {
printk(KERN_ERR "Spectra: Unable to remap memory region\n");
ret = -ENOMEM;
- goto failed_remap_csr;
+ goto failed_req_regions;
}
nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
(uint64_t)csr_base, denali->flash_reg, csr_len);
denali->flash_mem = ioremap_nocache(mem_base, mem_len);
if (!denali->flash_mem) {
printk(KERN_ERR "Spectra: ioremap_nocache failed!");
- iounmap(denali->flash_reg);
ret = -ENOMEM;
- goto failed_remap_csr;
+ goto failed_remap_reg;
}
nand_dbg_print(NAND_DBG_WARN,
DENALI_NAND_NAME, denali)) {
printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
ret = -ENODEV;
- goto failed_request_irq;
+ goto failed_remap_mem;
}
/* now that our ISR is registered, we can enable interrupts */
* with the nand subsystem */
if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
ret = -ENXIO;
- goto failed_nand;
+ goto failed_req_irq;
}
/* MTD supported page sizes vary by kernel. We validate our
ret = -ENODEV;
printk(KERN_ERR "Spectra: device size not supported by this "
"version of MTD.");
- goto failed_nand;
+ goto failed_req_irq;
}
+ /* support for multi nand
+ * MTD known nothing about multi nand,
+ * so we should tell it the real pagesize
+ * and anything necessery
+ */
+ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
+ denali->nand.chipsize <<= (denali->devnum - 1);
+ denali->nand.page_shift += (denali->devnum - 1);
+ denali->nand.pagemask = (denali->nand.chipsize >>
+ denali->nand.page_shift) - 1;
+ denali->nand.bbt_erase_shift += (denali->devnum - 1);
+ denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
+ denali->nand.chip_shift += (denali->devnum - 1);
+ denali->mtd.writesize <<= (denali->devnum - 1);
+ denali->mtd.oobsize <<= (denali->devnum - 1);
+ denali->mtd.erasesize <<= (denali->devnum - 1);
+ denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
+ denali->bbtskipbytes *= denali->devnum;
+
/* second stage of the NAND scan
* this stage requires information regarding ECC and
* bad block management. */
denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
- if (denali->nand.cellinfo & 0xc) {
- denali->nand.ecc.layout = &nand_oob_mlc_14bit;
- denali->nand.ecc.bytes = ECC_BYTES_MLC;
- } else {/* SLC */
- denali->nand.ecc.layout = &nand_oob_slc;
- denali->nand.ecc.bytes = ECC_BYTES_SLC;
+ /* Denali Controller only support 15bit and 8bit ECC in MRST,
+ * so just let controller do 15bit ECC for MLC and 8bit ECC for
+ * SLC if possible.
+ * */
+ if (denali->nand.cellinfo & 0xc &&
+ (denali->mtd.oobsize > (denali->bbtskipbytes +
+ ECC_15BITS * (denali->mtd.writesize /
+ ECC_SECTOR_SIZE)))) {
+ /* if MLC OOB size is large enough, use 15bit ECC*/
+ denali->nand.ecc.layout = &nand_15bit_oob;
+ denali->nand.ecc.bytes = ECC_15BITS;
+ denali_write32(15, denali->flash_reg + ECC_CORRECTION);
+ } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
+ ECC_8BITS * (denali->mtd.writesize /
+ ECC_SECTOR_SIZE))) {
+ printk(KERN_ERR "Your NAND chip OOB is not large enough to"
+ " contain 8bit ECC correction codes");
+ goto failed_req_irq;
+ } else {
+ denali->nand.ecc.layout = &nand_8bit_oob;
+ denali->nand.ecc.bytes = ECC_8BITS;
+ denali_write32(8, denali->flash_reg + ECC_CORRECTION);
}
+ denali->nand.ecc.bytes *= denali->devnum;
+ denali->nand.ecc.layout->eccbytes *=
+ denali->mtd.writesize / ECC_SECTOR_SIZE;
+ denali->nand.ecc.layout->oobfree[0].offset =
+ denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
+ denali->nand.ecc.layout->oobfree[0].length =
+ denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
+ denali->bbtskipbytes;
+
/* Let driver know the total blocks number and
* how many blocks contained by each nand chip.
* blksperchip will help driver to know how many
denali->nand.ecc.hwctl = denali_ecc_hwctl;
/* override the default read operations */
- denali->nand.ecc.size = denali->mtd.writesize;
+ denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
denali->nand.ecc.read_page = denali_read_page;
denali->nand.ecc.read_page_raw = denali_read_page_raw;
denali->nand.ecc.write_page = denali_write_page;
if (nand_scan_tail(&denali->mtd)) {
ret = -ENXIO;
- goto failed_nand;
+ goto failed_req_irq;
}
ret = add_mtd_device(&denali->mtd);
if (ret) {
printk(KERN_ERR "Spectra: Failed to register"
" MTD device: %d\n", ret);
- goto failed_nand;
+ goto failed_req_irq;
}
return 0;
- failed_nand:
+failed_req_irq:
denali_irq_cleanup(dev->irq, denali);
- failed_request_irq:
- iounmap(denali->flash_reg);
+failed_remap_mem:
iounmap(denali->flash_mem);
- failed_remap_csr:
+failed_remap_reg:
+ iounmap(denali->flash_reg);
+failed_req_regions:
pci_release_regions(dev);
- failed_req_csr:
+failed_dma_map:
pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
PCI_DMA_BIDIRECTIONAL);
- failed_enable:
+failed_enable_dev:
+ pci_disable_device(dev);
+failed_alloc_memery:
kfree(denali);
return ret;
}
projects / cascardo / linux.git / blobdiff