#include <asm/processor.h>
#define DRV_NAME "r6040"
-#define DRV_VERSION "0.21"
-#define DRV_RELDATE "09Jan2009"
+#define DRV_VERSION "0.22"
+#define DRV_RELDATE "25Mar2009"
/* PHY CHIP Address */
#define PHY1_ADDR 1 /* For MAC1 */
-#define PHY2_ADDR 2 /* For MAC2 */
+#define PHY2_ADDR 3 /* For MAC2 */
#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
/* Free Descriptor memory */
if (lp->rx_ring) {
pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
- lp->rx_ring = 0;
+ lp->rx_ring = NULL;
}
if (lp->tx_ring) {
pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
- lp->tx_ring = 0;
+ lp->tx_ring = NULL;
}
return 0;
work_done = r6040_rx(dev, budget);
if (work_done < budget) {
- netif_rx_complete(napi);
+ napi_complete(napi);
/* Enable RX interrupt */
iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
}
/* Mask off RX interrupt */
misr &= ~RX_INTS;
- netif_rx_schedule(&lp->napi);
+ napi_schedule(&lp->napi);
}
/* TX interrupt request */