#include <asm/processor.h>
#define DRV_NAME "r6040"
-#define DRV_VERSION "0.18"
-#define DRV_RELDATE "13Jul2008"
+#define DRV_VERSION "0.19"
+#define DRV_RELDATE "18Dec2008"
/* PHY CHIP Address */
#define PHY1_ADDR 1 /* For MAC1 */
/* Wait for the read bit to be cleared */
while (limit--) {
cmd = ioread16(ioaddr + MMDIO);
- if (cmd & MDIO_READ)
+ if (!(cmd & MDIO_READ))
break;
}
/* Wait for the write bit to be cleared */
while (limit--) {
cmd = ioread16(ioaddr + MMDIO);
- if (cmd & MDIO_WRITE)
+ if (!(cmd & MDIO_WRITE))
break;
}
}
work_done = r6040_rx(dev, budget);
if (work_done < budget) {
- netif_rx_complete(dev, napi);
+ netif_rx_complete(napi);
/* Enable RX interrupt */
iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
}
struct net_device *dev = dev_id;
struct r6040_private *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
- u16 status;
+ u16 misr, status;
+ /* Save MIER */
+ misr = ioread16(ioaddr + MIER);
/* Mask off RDC MAC interrupt */
iowrite16(MSK_INT, ioaddr + MIER);
/* Read MISR status and clear */
dev->stats.rx_fifo_errors++;
/* Mask off RX interrupt */
- iowrite16(ioread16(ioaddr + MIER) & ~RX_INTS, ioaddr + MIER);
- netif_rx_schedule(dev, &lp->napi);
+ misr &= ~RX_INTS;
+ netif_rx_schedule(&lp->napi);
}
/* TX interrupt request */
if (status & TX_INTS)
r6040_tx(dev);
+ /* Restore RDC MAC interrupt */
+ iowrite16(misr, ioaddr + MIER);
+
return IRQ_HANDLED;
}