Merge git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next

[cascardo/linux.git] / drivers / net / wireless / iwlwifi / iwl-prph.h

diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index a70c7b9..9c90186 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -5,7 +5,7 @@
  *
  * GPL LICENSE SUMMARY
  *
- * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
+ * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of version 2 of the GNU General Public License as
@@ -30,7 +30,7 @@
  *
  * BSD LICENSE
  *
- * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
+ * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -102,6 +102,16 @@
 /* Device system time */
 #define DEVICE_SYSTEM_TIME_REG 0xA0206C
 
+/* Device NMI register */
+#define DEVICE_SET_NMI_REG 0x00a01c30
+
+/*
+ * Device reset for family 8000
+ * write to bit 24 in order to reset the CPU
+*/
+#define RELEASE_CPU_RESET              (0x300C)
+#define RELEASE_CPU_RESET_BIT          BIT(24)
+
 /*****************************************************************************
  *                        7000/3000 series SHR DTS addresses                 *
  *****************************************************************************/
@@ -274,4 +284,47 @@ static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
 
 /*********************** END TX SCHEDULER *************************************/
 
+/* Oscillator clock */
+#define OSC_CLK                                (0xa04068)
+#define OSC_CLK_FORCE_CONTROL          (0x8)
+
+/* SECURE boot registers */
+#define LMPM_SECURE_BOOT_CONFIG_ADDR   (0x100)
+enum secure_boot_config_reg {
+       LMPM_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
+       LMPM_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ       = 0x00000002,
+};
+
+#define LMPM_SECURE_BOOT_CPU1_STATUS_ADDR      (0x1E30)
+#define LMPM_SECURE_BOOT_CPU2_STATUS_ADDR      (0x1E34)
+enum secure_boot_status_reg {
+       LMPM_SECURE_BOOT_CPU_STATUS_VERF_STATUS         = 0x00000001,
+       LMPM_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED      = 0x00000002,
+       LMPM_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS        = 0x00000004,
+       LMPM_SECURE_BOOT_CPU_STATUS_VERF_FAIL           = 0x00000008,
+       LMPM_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL      = 0x00000010,
+       LMPM_SECURE_BOOT_STATUS_SUCCESS                 = 0x00000003,
+};
+
+#define CSR_UCODE_LOAD_STATUS_ADDR     (0x1E70)
+enum secure_load_status_reg {
+       LMPM_CPU_UCODE_LOADING_STARTED                  = 0x00000001,
+       LMPM_CPU_HDRS_LOADING_COMPLETED                 = 0x00000003,
+       LMPM_CPU_UCODE_LOADING_COMPLETED                = 0x00000007,
+       LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED           = 0x000000F8,
+       LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK        = 0x0000FF00,
+};
+
+#define LMPM_SECURE_INSPECTOR_CODE_ADDR        (0x1E38)
+#define LMPM_SECURE_INSPECTOR_DATA_ADDR        (0x1E3C)
+#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR   (0x1E78)
+#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR   (0x1E7C)
+
+#define LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE   (0x400000)
+#define LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE   (0x402000)
+#define LMPM_SECURE_CPU1_HDR_MEM_SPACE         (0x420000)
+#define LMPM_SECURE_CPU2_HDR_MEM_SPACE         (0x420400)
+
+#define LMPM_SECURE_TIME_OUT   (100)
+
 #endif                         /* __iwl_prph_h__ */