u8 cs;
u16 void_write_data;
u32 cs_change;
- struct fsl_dspi_devtype_data *devtype_data;
+ const struct fsl_dspi_devtype_data *devtype_data;
wait_queue_head_t waitq;
u32 waitflags;
{
struct spi_master *master = dev_get_drvdata(dev);
struct fsl_dspi *dspi = spi_master_get_devdata(master);
+ int ret;
pinctrl_pm_select_default_state(dev);
- clk_prepare_enable(dspi->clk);
+ ret = clk_prepare_enable(dspi->clk);
+ if (ret)
+ return ret;
spi_master_resume(master);
return 0;
struct resource *res;
void __iomem *base;
int ret = 0, cs_num, bus_num;
- const struct of_device_id *of_id =
- of_match_device(fsl_dspi_dt_ids, &pdev->dev);
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
if (!master)
}
master->bus_num = bus_num;
- dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data;
+ dspi->devtype_data = of_device_get_match_data(&pdev->dev);
if (!dspi->devtype_data) {
dev_err(&pdev->dev, "can't get devtype_data\n");
ret = -EFAULT;
dev_err(&pdev->dev, "unable to get clock\n");
goto out_master_put;
}
- clk_prepare_enable(dspi->clk);
+ ret = clk_prepare_enable(dspi->clk);
+ if (ret)
+ goto out_master_put;
master->max_speed_hz =
clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
/* Disconnect from the SPI framework */
clk_disable_unprepare(dspi->clk);
spi_unregister_master(dspi->master);
- spi_master_put(dspi->master);
return 0;
}