return (bits >> ((channel % 3) * 5)) & 0x1f;
};
-enum MSeries_Gi_DMA_Config_Bits {
- Gi_DMA_BankSW_Error_Bit = 0x10,
- Gi_DMA_Reset_Bit = 0x8,
- Gi_DMA_Int_Enable_Bit = 0x4,
- Gi_DMA_Write_Bit = 0x2,
- Gi_DMA_Enable_Bit = 0x1,
-};
-
static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
{
return 0x3 << (channel * 2);
const struct comedi_lrange *ao_range_table;
unsigned ao_speed;
- unsigned num_p0_dio_channels;
-
int reg_type;
unsigned int has_8255:1;
+ unsigned int has_32dio_chan:1;
enum caldac_enum caldac[3];
};