/* Macros to access registers */
-/* Reset board */
-#define RtdResetBoard(dev) \
- writel(0, devpriv->las0+LAS0_BOARD_RESET)
-
-/* Reset channel gain table read pointer */
-#define RtdResetCGT(dev) \
- writel(0, devpriv->las0+LAS0_CGT_RESET)
-
-/* Reset channel gain table read and write pointers */
-#define RtdClearCGT(dev) \
- writel(0, devpriv->las0+LAS0_CGT_CLEAR)
-
-/* Reset channel gain table read and write pointers */
-#define RtdEnableCGT(dev, v) \
- writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
-
-/* Write channel gain table entry */
-#define RtdWriteCGTable(dev, v) \
- writel(v, devpriv->las0+LAS0_CGT_WRITE)
-
-/* Write Channel Gain Latch */
-#define RtdWriteCGLatch(dev, v) \
- writel(v, devpriv->las0+LAS0_CGL_WRITE)
-
-/* Reset ADC FIFO */
-#define RtdAdcClearFifo(dev) \
- writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
-
-/* Set ADC start conversion source select (write only) */
-#define RtdAdcConversionSource(dev, v) \
- writel(v, devpriv->las0+LAS0_ADC_CONVERSION)
-
-/* Set burst start source select (write only) */
-#define RtdBurstStartSource(dev, v) \
- writel(v, devpriv->las0+LAS0_BURST_START)
-
-/* Set Pacer start source select (write only) */
-#define RtdPacerStartSource(dev, v) \
- writel(v, devpriv->las0+LAS0_PACER_START)
-
-/* Set Pacer stop source select (write only) */
-#define RtdPacerStopSource(dev, v) \
- writel(v, devpriv->las0+LAS0_PACER_STOP)
-
-/* Set Pacer clock source select (write only) 0=external 1=internal */
-#define RtdPacerClockSource(dev, v) \
- writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_SELECT)
-
-/* Set sample counter source select (write only) */
-#define RtdAdcSampleCounterSource(dev, v) \
- writel(v, devpriv->las0+LAS0_ADC_SCNT_SRC)
-
-/* Set Pacer trigger mode select (write only) 0=single cycle, 1=repeat */
-#define RtdPacerTriggerMode(dev, v) \
- writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_PACER_REPEAT)
-
-/* Set About counter stop enable (write only) */
-#define RtdAboutStopEnable(dev, v) \
- writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ACNT_STOP_ENABLE)
-
-/* Set external trigger polarity (write only) 0=positive edge, 1=negative */
-#define RtdTriggerPolarity(dev, v) \
- writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_ETRG_POLARITY)
-
-/* Start single ADC conversion */
-#define RtdAdcStart(dev) \
- writew(0, devpriv->las0+LAS0_ADC)
-
-/* Read one ADC data value (12bit (with sign extend) as 16bit) */
-/* Note: matches what DMA would get. Actual value >> 3 */
-#define RtdAdcFifoGet(dev) \
- readw(devpriv->las1+LAS1_ADC_FIFO)
-
-/* Read two ADC data values (DOESN'T WORK) */
-#define RtdAdcFifoGet2(dev) \
- readl(devpriv->las1+LAS1_ADC_FIFO)
-
-/* FIFO status */
-#define RtdFifoStatus(dev) \
- readl(devpriv->las0+LAS0_ADC)
-
-/* pacer start/stop read=start, write=stop*/
-#define RtdPacerStart(dev) \
- readl(devpriv->las0+LAS0_PACER)
-#define RtdPacerStop(dev) \
- writel(0, devpriv->las0+LAS0_PACER)
-
-/* Interrupt status */
-#define RtdInterruptStatus(dev) \
- readw(devpriv->las0+LAS0_IT)
-
-/* Interrupt mask */
-#define RtdInterruptMask(dev, v) \
- writew((devpriv->intMask = (v)), devpriv->las0+LAS0_IT)
-
-/* Interrupt status clear (only bits set in mask) */
-#define RtdInterruptClear(dev) \
- readw(devpriv->las0+LAS0_CLEAR)
-
-/* Interrupt clear mask */
-#define RtdInterruptClearMask(dev, v) \
- writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
-
-/* Interrupt overrun status */
-#define RtdInterruptOverrunStatus(dev) \
- readl(devpriv->las0+LAS0_OVERRUN)
-
-/* Interrupt overrun clear */
-#define RtdInterruptOverrunClear(dev) \
- writel(0, devpriv->las0+LAS0_OVERRUN)
-
-/* Pacer counter, 24bit */
-#define RtdPacerCount(dev) \
- readl(devpriv->las0+LAS0_PCLK)
-#define RtdPacerCounter(dev, v) \
- writel((v) & 0xffffff, devpriv->las0+LAS0_PCLK)
-
-/* Burst counter, 10bit */
-#define RtdBurstCount(dev) \
- readl(devpriv->las0+LAS0_BCLK)
-#define RtdBurstCounter(dev, v) \
- writel((v) & 0x3ff, devpriv->las0+LAS0_BCLK)
-
-/* Delay counter, 16bit */
-#define RtdDelayCount(dev) \
- readl(devpriv->las0+LAS0_DCLK)
-#define RtdDelayCounter(dev, v) \
- writel((v) & 0xffff, devpriv->las0+LAS0_DCLK)
-
-/* About counter, 16bit */
-#define RtdAboutCount(dev) \
- readl(devpriv->las0+LAS0_ACNT)
-#define RtdAboutCounter(dev, v) \
- writel((v) & 0xffff, devpriv->las0+LAS0_ACNT)
-
-/* ADC sample counter, 10bit */
-#define RtdAdcSampleCount(dev) \
- readl(devpriv->las0+LAS0_ADC_SCNT)
-#define RtdAdcSampleCounter(dev, v) \
- writel((v) & 0x3ff, devpriv->las0+LAS0_ADC_SCNT)
-
-/* User Timer/Counter (8254) */
-#define RtdUtcCounterGet(dev, n) \
- readb(devpriv->las0 \
- + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
-
-#define RtdUtcCounterPut(dev, n, v) \
- writeb((v) & 0xff, devpriv->las0 \
- + ((n <= 0) ? LAS0_UTC0 : ((1 == n) ? LAS0_UTC1 : LAS0_UTC2)))
-
-/* Set UTC (8254) control byte */
-#define RtdUtcCtrlPut(dev, n, v) \
- writeb(devpriv->utcCtrl[(n) & 3] = (((n) & 3) << 6) | ((v) & 0x3f), \
- devpriv->las0 + LAS0_UTC_CTRL)
-
-/* Set UTCn clock source (write only) */
-#define RtdUtcClockSource(dev, n, v) \
- writew(v, devpriv->las0 \
- + ((n <= 0) ? LAS0_UTC0_CLOCK : \
- ((1 == n) ? LAS0_UTC1_CLOCK : LAS0_UTC2_CLOCK)))
-
-/* Set UTCn gate source (write only) */
-#define RtdUtcGateSource(dev, n, v) \
- writew(v, devpriv->las0 \
- + ((n <= 0) ? LAS0_UTC0_GATE : \
- ((1 == n) ? LAS0_UTC1_GATE : LAS0_UTC2_GATE)))
-
-/* User output N source select (write only) */
-#define RtdUsrOutSource(dev, n, v) \
- writel(v, devpriv->las0+((n <= 0) ? LAS0_UOUT0_SELECT : \
- LAS0_UOUT1_SELECT))
-
-/* Digital IO */
-#define RtdDio0Read(dev) \
- (readw(devpriv->las0+LAS0_DIO0) & 0xff)
-#define RtdDio0Write(dev, v) \
- writew((v) & 0xff, devpriv->las0+LAS0_DIO0)
-
-#define RtdDio1Read(dev) \
- (readw(devpriv->las0+LAS0_DIO1) & 0xff)
-#define RtdDio1Write(dev, v) \
- writew((v) & 0xff, devpriv->las0+LAS0_DIO1)
-
-#define RtdDioStatusRead(dev) \
- (readw(devpriv->las0+LAS0_DIO_STATUS) & 0xff)
-#define RtdDioStatusWrite(dev, v) \
- writew((devpriv->dioStatus = (v)), devpriv->las0+LAS0_DIO_STATUS)
-
-#define RtdDio0CtrlRead(dev) \
- (readw(devpriv->las0+LAS0_DIO0_CTRL) & 0xff)
-#define RtdDio0CtrlWrite(dev, v) \
- writew((v) & 0xff, devpriv->las0+LAS0_DIO0_CTRL)
-
-/* Digital to Analog converter */
-/* Write one data value (sign + 12bit + marker bits) */
-/* Note: matches what DMA would put. Actual value << 3 */
-#define RtdDacFifoPut(dev, n, v) \
- writew((v), devpriv->las1 + (((n) == 0) ? LAS1_DAC1_FIFO : \
- LAS1_DAC2_FIFO))
-
-/* Start single DAC conversion */
-#define RtdDacUpdate(dev, n) \
- writew(0, devpriv->las0 + (((n) == 0) ? LAS0_DAC1 : LAS0_DAC2))
-
-/* Start single DAC conversion on both DACs */
-#define RtdDacBothUpdate(dev) \
- writew(0, devpriv->las0+LAS0_DAC)
-
-/* Set DAC output type and range */
-#define RtdDacRange(dev, n, v) \
- writew((v) & 7, devpriv->las0 \
- +(((n) == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL))
-
-/* Reset DAC FIFO */
-#define RtdDacClearFifo(dev, n) \
- writel(0, devpriv->las0+(((n) == 0) ? LAS0_DAC1_RESET : \
- LAS0_DAC2_RESET))
-
-/* Set source for DMA 0 (write only, shadow?) */
-#define RtdDma0Source(dev, n) \
- writel((n) & 0xf, devpriv->las0+LAS0_DMA0_SRC)
-
-/* Set source for DMA 1 (write only, shadow?) */
-#define RtdDma1Source(dev, n) \
- writel((n) & 0xf, devpriv->las0+LAS0_DMA1_SRC)
-
-/* Reset board state for DMA 0 */
-#define RtdDma0Reset(dev) \
- writel(0, devpriv->las0+LAS0_DMA0_RESET)
-
-/* Reset board state for DMA 1 */
-#define RtdDma1Reset(dev) \
- writel(0, devpriv->las0+LAS0_DMA1_SRC)
-
-/* PLX9080 interrupt mask and status */
-#define RtdPlxInterruptRead(dev) \
- readl(devpriv->lcfg+LCFG_ITCSR)
-#define RtdPlxInterruptWrite(dev, v) \
- writel(v, devpriv->lcfg+LCFG_ITCSR)
-
-/* Set mode for DMA 0 */
-#define RtdDma0Mode(dev, m) \
- writel((m), devpriv->lcfg+LCFG_DMAMODE0)
-
-/* Set PCI address for DMA 0 */
-#define RtdDma0PciAddr(dev, a) \
- writel((a), devpriv->lcfg+LCFG_DMAPADR0)
-
-/* Set local address for DMA 0 */
-#define RtdDma0LocalAddr(dev, a) \
- writel((a), devpriv->lcfg+LCFG_DMALADR0)
-
/* Set byte count for DMA 0 */
#define RtdDma0Count(dev, c) \
writel((c), devpriv->lcfg+LCFG_DMASIZ0)
{
if (n_chan > 1) { /* setup channel gain table */
int ii;
- RtdClearCGT(dev);
- RtdEnableCGT(dev, 1); /* enable table */
+
+ writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
+ writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
for (ii = 0; ii < n_chan; ii++) {
- RtdWriteCGTable(dev, rtdConvertChanGain(dev, list[ii],
- ii));
+ writel(rtdConvertChanGain(dev, list[ii], ii),
+ devpriv->las0 + LAS0_CGT_WRITE);
}
} else { /* just use the channel gain latch */
- RtdEnableCGT(dev, 0); /* disable table, enable latch */
- RtdWriteCGLatch(dev, rtdConvertChanGain(dev, list[0], 0));
+ writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
+ writel(rtdConvertChanGain(dev, list[0], 0),
+ devpriv->las0 + LAS0_CGL_WRITE);
}
}
static const unsigned limit = 0x2000;
unsigned fifo_size = 0;
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
rtd_load_channelgain_list(dev, 1, &chanspec);
- RtdAdcConversionSource(dev, 0); /* software */
+ writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
/* convert samples */
for (i = 0; i < limit; ++i) {
unsigned fifo_status;
/* trigger conversion */
- RtdAdcStart(dev);
+ writew(0, devpriv->las0 + LAS0_ADC);
udelay(1);
- fifo_status = RtdFifoStatus(dev);
+ fifo_status = readl(devpriv->las0 + LAS0_ADC);
if ((fifo_status & FS_ADC_HEMPTY) == 0) {
fifo_size = 2 * i;
break;
DRV_NAME);
return -EIO;
}
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
if (fifo_size != 0x400 && fifo_size != 0x2000) {
printk
(KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
int stat;
/* clear any old fifo data */
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
/* write channel to multiplexer and clear channel gain table */
rtd_load_channelgain_list(dev, 1, &insn->chanspec);
/* set conversion source */
- RtdAdcConversionSource(dev, 0); /* software */
+ writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
/* convert n samples */
for (n = 0; n < insn->n; n++) {
s16 d;
/* trigger conversion */
- RtdAdcStart(dev);
+ writew(0, devpriv->las0 + LAS0_ADC);
for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
- stat = RtdFifoStatus(dev);
+ stat = readl(devpriv->las0 + LAS0_ADC);
if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
break;
WAIT_QUIETLY;
}
/* read data */
- d = RtdAdcFifoGet(dev); /* get 2s comp value */
+ d = readw(devpriv->las1 + LAS1_ADC_FIFO);
/*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
d = d >> 3; /* low 3 bits are marker lines */
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
s16 d;
if (0 == devpriv->aiCount) { /* done */
- d = RtdAdcFifoGet(dev); /* Read N and discard */
+ d = readw(devpriv->las1 + LAS1_ADC_FIFO);
continue;
}
#if 0
- if (0 == (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY)) { /* DEBUG */
+ if (!(readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY)) {
DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
count);
break;
}
#endif
- d = RtdAdcFifoGet(dev); /* get 2s comp value */
+ d = readw(devpriv->las1 + LAS1_ADC_FIFO);
d = d >> 3; /* low 3 bits are marker lines */
if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
*/
static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
{
- while (RtdFifoStatus(dev) & FS_ADC_NOT_EMPTY) { /* 1 -> not empty */
+ while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
short sample;
- s16 d = RtdAdcFifoGet(dev); /* get 2s comp value */
+ s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
if (0 == devpriv->aiCount) { /* done */
continue; /* read rest */
void *d)
{ /* our data *//* cpu context (ignored) */
struct comedi_device *dev = d; /* must be called "dev" for devpriv */
+ struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
+ u32 overrun;
u16 status;
u16 fifoStatus;
- struct comedi_subdevice *s = dev->subdevices + 0; /* analog in subdevice */
if (!dev->attached)
return IRQ_NONE;
devpriv->intCount++; /* DEBUG statistics */
- fifoStatus = RtdFifoStatus(dev);
+ fifoStatus = readl(devpriv->las0 + LAS0_ADC);
/* check for FIFO full, this automatically halts the ADC! */
if (!(fifoStatus & FS_ADC_NOT_FULL)) { /* 0 -> full */
DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777); /* should be all 0s */
}
#ifdef USE_DMA
if (devpriv->flags & DMA0_ACTIVE) { /* Check DMA */
- u32 istatus = RtdPlxInterruptRead(dev);
+ u32 istatus = readl(devpriv->lcfg + LCFG_ITCSR);
if (istatus & ICS_DMA0_A) {
if (ai_process_dma(dev, s) < 0) {
/* Fall through and check for other interrupt sources */
#endif /* USE_DMA */
- status = RtdInterruptStatus(dev);
+ status = readw(devpriv->las0 + LAS0_IT);
/* if interrupt was not caused by our board, or handled above */
if (0 == status)
return IRQ_HANDLED;
DPRINTK("rtd520: unknown interrupt source!\n");
}
- if (0xffff & RtdInterruptOverrunStatus(dev)) { /* interrupt overrun */
+ overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
+ if (overrun) {
DPRINTK
("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
- devpriv->aiCount, 0xffff & RtdInterruptOverrunStatus(dev));
+ devpriv->aiCount, overrun);
goto abortTransfer;
}
/* clear the interrupt */
- RtdInterruptClearMask(dev, status);
- RtdInterruptClear(dev);
+ devpriv->intClearMask = status;
+ writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
+ readw(devpriv->las0 + LAS0_CLEAR);
return IRQ_HANDLED;
abortTransfer:
- RtdAdcClearFifo(dev); /* clears full flag */
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
s->async->events |= COMEDI_CB_ERROR;
devpriv->aiCount = 0; /* stop and don't transfer any more */
/* fall into transferDone */
transferDone:
- RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
- RtdPacerStop(dev); /* Stop PACER */
- RtdAdcConversionSource(dev, 0); /* software trigger only */
- RtdInterruptMask(dev, 0); /* mask out SAMPLE */
+ writel(0, devpriv->las0 + LAS0_PACER_STOP);
+ writel(0, devpriv->las0 + LAS0_PACER);
+ writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
+ devpriv->intMask = 0;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
#ifdef USE_DMA
if (devpriv->flags & DMA0_ACTIVE) {
- RtdPlxInterruptWrite(dev, /* disable any more interrupts */
- RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) & ~ICS_DMA0_E,
+ devpriv->lcfg + LCFG_ITCSR);
abort_dma(dev, 0);
devpriv->flags &= ~DMA0_ACTIVE;
/* if Using DMA, then we should have read everything by now */
#endif /* USE_DMA */
if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
- fifoStatus = RtdFifoStatus(dev);
+ fifoStatus = readl(devpriv->las0 + LAS0_ADC);
DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777); /* should read all 0s */
ai_read_dregs(dev, s); /* read anything left in FIFO */
}
comedi_event(dev, s);
/* clear the interrupt */
- status = RtdInterruptStatus(dev);
- RtdInterruptClearMask(dev, status);
- RtdInterruptClear(dev);
+ status = readw(devpriv->las0 + LAS0_IT);
+ devpriv->intClearMask = status;
+ writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
+ readw(devpriv->las0 + LAS0_CLEAR);
- fifoStatus = RtdFifoStatus(dev); /* DEBUG */
+ fifoStatus = readl(devpriv->las0 + LAS0_ADC);
+ overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
DPRINTK
("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
- devpriv->intCount, status,
- 0xffff & RtdInterruptOverrunStatus(dev));
+ devpriv->intCount, status, overrun);
return IRQ_HANDLED;
}
int timer;
/* stop anything currently running */
- RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
- RtdPacerStop(dev); /* make sure PACER is stopped */
- RtdAdcConversionSource(dev, 0); /* software trigger only */
- RtdInterruptMask(dev, 0);
+ writel(0, devpriv->las0 + LAS0_PACER_STOP);
+ writel(0, devpriv->las0 + LAS0_PACER);
+ writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
+ devpriv->intMask = 0;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
#ifdef USE_DMA
if (devpriv->flags & DMA0_ACTIVE) { /* cancel anything running */
- RtdPlxInterruptWrite(dev, /* disable any more interrupts */
- RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) & ~ICS_DMA0_E,
+ devpriv->lcfg + LCFG_ITCSR);
abort_dma(dev, 0);
devpriv->flags &= ~DMA0_ACTIVE;
- if (RtdPlxInterruptRead(dev) & ICS_DMA0_A) { /*clear pending int */
+ if (readl(devpriv->lcfg + LCFG_ITCSR) & ICS_DMA0_A)
RtdDma0Control(dev, PLX_CLEAR_DMA_INTR_BIT);
- }
}
- RtdDma0Reset(dev); /* reset onboard state */
+ writel(0, devpriv->las0 + LAS0_DMA0_RESET);
#endif /* USE_DMA */
- RtdAdcClearFifo(dev); /* clear any old data */
- RtdInterruptOverrunClear(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
+ writel(0, devpriv->las0 + LAS0_OVERRUN);
devpriv->intCount = 0;
if (!dev->irq) { /* we need interrupts for this */
/* setup the common case and override if needed */
if (cmd->chanlist_len > 1) {
/*DPRINTK ("rtd520: Multi channel setup\n"); */
- RtdPacerStartSource(dev, 0); /* software triggers pacer */
- RtdBurstStartSource(dev, 1); /* PACER triggers burst */
- RtdAdcConversionSource(dev, 2); /* BURST triggers ADC */
+ writel(0, devpriv->las0 + LAS0_PACER_START);
+ writel(1, devpriv->las0 + LAS0_BURST_START);
+ writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
} else { /* single channel */
/*DPRINTK ("rtd520: single channel setup\n"); */
- RtdPacerStartSource(dev, 0); /* software triggers pacer */
- RtdAdcConversionSource(dev, 1); /* PACER triggers ADC */
+ writel(0, devpriv->las0 + LAS0_PACER_START);
+ writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
}
- RtdAboutCounter(dev, devpriv->fifoLen / 2 - 1); /* 1/2 FIFO */
+ writel((devpriv->fifoLen / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
if (TRIG_TIMER == cmd->scan_begin_src) {
/* scan_begin_arg is in nanoseconds */
devpriv->flags &= ~SEND_EOS;
} else {
/* interrupt for each transfer */
- RtdAboutCounter(dev, devpriv->transCount - 1);
+ writel((devpriv->transCount - 1) & 0xffff,
+ devpriv->las0 + LAS0_ACNT);
}
DPRINTK
devpriv->transCount = 0;
devpriv->flags &= ~SEND_EOS;
}
- RtdPacerClockSource(dev, 1); /* use INTERNAL 8Mhz clock source */
- RtdAboutStopEnable(dev, 1); /* just interrupt, dont stop */
+ writel(1, devpriv->las0 + LAS0_PACER_SELECT);
+ writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
/* BUG??? these look like enumerated values, but they are bit fields */
TRIG_ROUND_NEAREST);
/* set PACER clock */
/*DPRINTK ("rtd520: loading %d into pacer\n", timer); */
- RtdPacerCounter(dev, timer);
+ writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
break;
case TRIG_EXT:
- RtdPacerStartSource(dev, 1); /* EXTERNALy trigger pacer */
+ writel(1, devpriv->las0 + LAS0_PACER_START);
break;
default:
TRIG_ROUND_NEAREST);
/* setup BURST clock */
/*DPRINTK ("rtd520: loading %d into burst\n", timer); */
- RtdBurstCounter(dev, timer);
+ writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
}
break;
case TRIG_EXT: /* external */
- RtdBurstStartSource(dev, 2); /* EXTERNALy trigger burst */
+ writel(2, devpriv->las0 + LAS0_BURST_START);
break;
default:
/* This doesn't seem to work. There is no way to clear an interrupt
that the priority controller has queued! */
- RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
- RtdInterruptClear(dev);
+ devpriv->intClearMask = ~0;
+ writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
+ readw(devpriv->las0 + LAS0_CLEAR);
/* TODO: allow multiple interrupt sources */
if (devpriv->transCount > 0) { /* transfer every N samples */
- RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
+ devpriv->intMask = IRQM_ADC_ABOUT_CNT;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
DPRINTK("rtd520: Transferring every %d\n", devpriv->transCount);
} else { /* 1/2 FIFO transfers */
#ifdef USE_DMA
/* point to first transfer in ring */
devpriv->dma0Offset = 0;
- RtdDma0Mode(dev, DMA_MODE_BITS);
+ writel(DMA_MODE_BITS, devpriv->lcfg + LCFG_DMAMODE0);
RtdDma0Next(dev, /* point to first block */
devpriv->dma0Chain[DMA_CHAIN_COUNT - 1].next);
- RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL); /* set DMA trigger source */
-
- RtdPlxInterruptWrite(dev, /* enable interrupt */
- RtdPlxInterruptRead(dev) | ICS_DMA0_E);
+ writel(DMAS_ADFIFO_HALF_FULL, devpriv->las0 + LAS0_DMA0_SRC);
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) | ICS_DMA0_E,
+ devpriv->lcfg + LCFG_ITCSR);
/* Must be 2 steps. See PLX app note about "Starting a DMA transfer" */
RtdDma0Control(dev, PLX_DMA_EN_BIT); /* enable DMA (clear INTR?) */
RtdDma0Control(dev, PLX_DMA_EN_BIT | PLX_DMA_START_BIT); /*start DMA */
DPRINTK("rtd520: Using DMA0 transfers. plxInt %x RtdInt %x\n",
- RtdPlxInterruptRead(dev), devpriv->intMask);
+ readl(devpriv->lcfg + LCFG_ITCSR), devpriv->intMask);
#else /* USE_DMA */
- RtdInterruptMask(dev, IRQM_ADC_ABOUT_CNT);
+ devpriv->intMask = IRQM_ADC_ABOUT_CNT;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
DPRINTK("rtd520: Transferring every 1/2 FIFO\n");
#endif /* USE_DMA */
}
/* BUG: start_src is ASSUMED to be TRIG_NOW */
/* BUG? it seems like things are running before the "start" */
- RtdPacerStart(dev); /* Start PACER */
+ readl(devpriv->las0 + LAS0_PACER);
return 0;
}
*/
static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
{
+ u32 overrun;
u16 status;
- RtdPacerStopSource(dev, 0); /* stop on SOFTWARE stop */
- RtdPacerStop(dev); /* Stop PACER */
- RtdAdcConversionSource(dev, 0); /* software trigger only */
- RtdInterruptMask(dev, 0);
+ writel(0, devpriv->las0 + LAS0_PACER_STOP);
+ writel(0, devpriv->las0 + LAS0_PACER);
+ writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
+ devpriv->intMask = 0;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
devpriv->aiCount = 0; /* stop and don't transfer any more */
#ifdef USE_DMA
if (devpriv->flags & DMA0_ACTIVE) {
- RtdPlxInterruptWrite(dev, /* disable any more interrupts */
- RtdPlxInterruptRead(dev) & ~ICS_DMA0_E);
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) & ~ICS_DMA0_E,
+ devpriv->lcfg + LCFG_ITCSR);
abort_dma(dev, 0);
devpriv->flags &= ~DMA0_ACTIVE;
}
#endif /* USE_DMA */
- status = RtdInterruptStatus(dev);
+ status = readw(devpriv->las0 + LAS0_IT);
+ overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
DPRINTK
("rtd520: Acquisition canceled. %ld ints, intStat=%x, overStat=%x\n",
- devpriv->intCount, status,
- 0xffff & RtdInterruptOverrunStatus(dev));
+ devpriv->intCount, status, overrun);
return 0;
}
int range = CR_RANGE(insn->chanspec);
/* Configure the output range (table index matches the range values) */
- RtdDacRange(dev, chan, range);
+ writew(range & 7, devpriv->las0 +
+ ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
/* Writing a list of values to an AO channel is probably not
* very useful, but that's how the interface is defined. */
chan, range, data[i], val);
/* a typical programming sequence */
- RtdDacFifoPut(dev, chan, val); /* put the value in */
- RtdDacUpdate(dev, chan); /* trigger the conversion */
+ writew(val, devpriv->las1 +
+ ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
+ writew(0, devpriv->las0 + ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
devpriv->aoValue[chan] = data[i]; /* save for read back */
for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
- stat = RtdFifoStatus(dev);
+ stat = readl(devpriv->las0 + LAS0_ADC);
/* 1 -> not empty */
if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
FS_DAC2_NOT_EMPTY))
s->state |= data[0] & data[1];
/* Write out the new digital output lines */
- RtdDio0Write(dev, s->state);
+ writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
}
/* on return, data[1] contains the value of the digital
* input lines. */
- data[1] = RtdDio0Read(dev);
+ data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
/*DPRINTK("rtd520:port_0 wrote: 0x%x read: 0x%x\n", s->state, data[1]); */
- return 2;
+ return insn->n;
}
/*
DPRINTK("rtd520: port_0_direction=0x%x (1 means out)\n", s->io_bits);
/* TODO support digital match interrupts and strobes */
- RtdDioStatusWrite(dev, 0x01); /* make Dio0Ctrl point to direction */
- RtdDio0CtrlWrite(dev, s->io_bits); /* set direction 1 means Out */
- RtdDioStatusWrite(dev, 0); /* make Dio0Ctrl clear interrupts */
+ devpriv->dioStatus = 0x01; /* set direction */
+ writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
+ writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
+ devpriv->dioStatus = 0x00; /* clear interrupts */
+ writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
/* port1 can only be all input or all output */
/* initialize board, per RTD spec */
/* also, initialize shadow registers */
- RtdResetBoard(dev);
+ writel(0, devpriv->las0 + LAS0_BOARD_RESET);
udelay(100); /* needed? */
- RtdPlxInterruptWrite(dev, 0);
- RtdInterruptMask(dev, 0); /* and sets shadow */
- RtdInterruptClearMask(dev, ~0); /* and sets shadow */
- RtdInterruptClear(dev); /* clears bits set by mask */
- RtdInterruptOverrunClear(dev);
- RtdClearCGT(dev);
- RtdAdcClearFifo(dev);
- RtdDacClearFifo(dev, 0);
- RtdDacClearFifo(dev, 1);
+ writel(0, devpriv->lcfg + LCFG_ITCSR);
+ devpriv->intMask = 0;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
+ devpriv->intClearMask = ~0;
+ writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
+ readw(devpriv->las0 + LAS0_CLEAR);
+ writel(0, devpriv->las0 + LAS0_OVERRUN);
+ writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
+ writel(0, devpriv->las0 + LAS0_DAC1_RESET);
+ writel(0, devpriv->las0 + LAS0_DAC2_RESET);
/* clear digital IO fifo */
- RtdDioStatusWrite(dev, 0); /* safe state, set shadow */
- RtdUtcCtrlPut(dev, 0, 0x30); /* safe state, set shadow */
- RtdUtcCtrlPut(dev, 1, 0x30); /* safe state, set shadow */
- RtdUtcCtrlPut(dev, 2, 0x30); /* safe state, set shadow */
- RtdUtcCtrlPut(dev, 3, 0); /* safe state, set shadow */
+ devpriv->dioStatus = 0;
+ writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
+ devpriv->utcCtrl[0] = (0 << 6) | 0x30;
+ devpriv->utcCtrl[1] = (1 << 6) | 0x30;
+ devpriv->utcCtrl[2] = (2 << 6) | 0x30;
+ devpriv->utcCtrl[3] = (3 << 6) | 0x00;
+ writeb(devpriv->utcCtrl[0], devpriv->las0 + LAS0_UTC_CTRL);
+ writeb(devpriv->utcCtrl[1], devpriv->las0 + LAS0_UTC_CTRL);
+ writeb(devpriv->utcCtrl[2], devpriv->las0 + LAS0_UTC_CTRL);
+ writeb(devpriv->utcCtrl[3], devpriv->las0 + LAS0_UTC_CTRL);
/* TODO: set user out source ??? */
/* check if our interrupt is available and get it */
goto rtd_attach_die_error;
}
- RtdDma0Mode(dev, DMA_MODE_BITS);
+ writel(DMA_MODE_BITS, devpriv->lcfg + LCFG_DMAMODE0);
/* set DMA trigger source */
- RtdDma0Source(dev, DMAS_ADFIFO_HALF_FULL);
+ writel(DMAS_ADFIFO_HALF_FULL, devpriv->las0 + LAS0_DMA0_SRC);
} else {
printk(KERN_INFO "( no IRQ->no DMA )");
}
#endif /* USE_DMA */
- if (dev->irq) { /* enable plx9080 interrupts */
- RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
- }
+ if (dev->irq)
+ writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + LCFG_ITCSR);
printk("\ncomedi%d: rtd520 driver attached.\n", dev->minor);
#endif /* USE_DMA */
/* subdevices and priv are freed by the core */
if (dev->irq) {
- /* disable interrupt controller */
- RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
- & ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E));
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) &
+ ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
+ devpriv->lcfg + LCFG_ITCSR);
free_irq(dev->irq, dev);
}
if (devpriv->lcfg) {
RtdDma0Control(dev, 0); /* disable DMA */
RtdDma1Control(dev, 0); /* disable DMA */
- RtdPlxInterruptWrite(dev, ICS_PIE | ICS_PLIE);
+ writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + LCFG_ITCSR);
}
#endif /* USE_DMA */
if (devpriv->las0) {
- RtdResetBoard(dev);
- RtdInterruptMask(dev, 0);
- RtdInterruptClearMask(dev, ~0);
- RtdInterruptClear(dev); /* clears bits set by mask */
+ writel(0, devpriv->las0 + LAS0_BOARD_RESET);
+ devpriv->intMask = 0;
+ writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
+ devpriv->intClearMask = ~0;
+ writew(devpriv->intClearMask,
+ devpriv->las0 + LAS0_CLEAR);
+ readw(devpriv->las0 + LAS0_CLEAR);
}
#ifdef USE_DMA
/* release DMA */
}
#endif /* USE_DMA */
if (dev->irq) {
- RtdPlxInterruptWrite(dev, RtdPlxInterruptRead(dev)
- & ~(ICS_PLIE | ICS_DMA0_E |
- ICS_DMA1_E));
+ writel(readl(devpriv->lcfg + LCFG_ITCSR) &
+ ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
+ devpriv->lcfg + LCFG_ITCSR);
free_irq(dev->irq, dev);
}
if (devpriv->las0)
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