x86: default to reboot via ACPI

[cascardo/linux.git] / include / asm-blackfin / mach-bf537 / cdefBF534.h

diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 78227bc..82de526 100644 (file)
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -44,7 +44,27 @@
 
 /* Clock and System Control    (0xFFC00000 - 0xFFC000FF)                                                               */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)              bfin_write16(PLL_CTL,val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+       unsigned long flags, iwr;
+
+       if (val == bfin_read_PLL_CTL())
+               return;
+
+       local_irq_save(flags);
+       /* Enable the PLL Wakeup bit in SIC IWR */
+       iwr = bfin_read32(SIC_IWR);
+       /* Only allow PPL Wakeup) */
+       bfin_write32(SIC_IWR, IWR_ENABLE(0));
+
+       bfin_write16(PLL_CTL, val);
+       SSYNC();
+       asm("IDLE;");
+
+       bfin_write32(SIC_IWR, iwr);
+       local_irq_restore(flags);
+}
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
 #define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
 #define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
@@ -53,6 +73,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 {
        unsigned long flags, iwr;
 
+       if (val == bfin_read_VR_CTL())
+               return;
+
+       local_irq_save(flags);
        /* Enable the PLL Wakeup bit in SIC IWR */
        iwr = bfin_read32(SIC_IWR);
        /* Only allow PPL Wakeup) */
@@ -60,11 +84,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 
        bfin_write16(VR_CTL, val);
        SSYNC();
-
-       local_irq_save(flags);
        asm("IDLE;");
-       local_irq_restore(flags);
+
        bfin_write32(SIC_IWR, iwr);
+       local_irq_restore(flags);
 }
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
 #define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
@@ -858,39 +881,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
 
-/* Two-Wire Interface          (0xFFC01400 - 0xFFC014FF)                                                               */
-#define bfin_read_TWI_CLKDIV()               bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)           bfin_write16(TWI_CLKDIV,val)
-#define bfin_read_TWI_CONTROL()              bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)          bfin_write16(TWI_CONTROL,val)
-#define bfin_read_TWI_SLAVE_CTL()            bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)        bfin_write16(TWI_SLAVE_CTL,val)
-#define bfin_read_TWI_SLAVE_STAT()           bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val)       bfin_write16(TWI_SLAVE_STAT,val)
-#define bfin_read_TWI_SLAVE_ADDR()           bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val)       bfin_write16(TWI_SLAVE_ADDR,val)
-#define bfin_read_TWI_MASTER_CTL()           bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val)       bfin_write16(TWI_MASTER_CTL,val)
-#define bfin_read_TWI_MASTER_STAT()          bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val)      bfin_write16(TWI_MASTER_STAT,val)
-#define bfin_read_TWI_MASTER_ADDR()          bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val)      bfin_write16(TWI_MASTER_ADDR,val)
-#define bfin_read_TWI_INT_STAT()             bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)         bfin_write16(TWI_INT_STAT,val)
-#define bfin_read_TWI_INT_MASK()             bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)         bfin_write16(TWI_INT_MASK,val)
-#define bfin_read_TWI_FIFO_CTL()             bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)         bfin_write16(TWI_FIFO_CTL,val)
-#define bfin_read_TWI_FIFO_STAT()            bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)        bfin_write16(TWI_FIFO_STAT,val)
-#define bfin_read_TWI_XMT_DATA8()            bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)        bfin_write16(TWI_XMT_DATA8,val)
-#define bfin_read_TWI_XMT_DATA16()           bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val)       bfin_write16(TWI_XMT_DATA16,val)
-#define bfin_read_TWI_RCV_DATA8()            bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)        bfin_write16(TWI_RCV_DATA8,val)
-#define bfin_read_TWI_RCV_DATA16()           bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val)       bfin_write16(TWI_RCV_DATA16,val)
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
 
 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                */
 #define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)